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Contents

README

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TL071CDR

Texas Instruments · FET InputAmplifiers · SOIC-8

TL071CDR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OFFSET N1 passive Offset null trim pin 1. Connect a potentiometer between OFFSET N1 (pin 1) and OFFSET N2 (pin 5) with the wiper tied to VCC- to trim the input offset voltage. Internal 1080 ohm resistors are tied here.
2 IN- input Inverting op-amp input. JFET input stage provides very high input impedance (~10^12 ohm) and very low input bias current (~65 pA typ).
3 IN+ input Non-inverting op-amp input. JFET input stage provides very high input impedance (~10^12 ohm) and very low input bias current (~65 pA typ). Common-mode range typically -12 V to +15 V on +/-15 V supplies.
4 VCC- power_in Negative supply rail. Rated down to -18 V absolute maximum; typically operated at -15 V (dual supply) or GND (single supply).
5 OFFSET N2 passive Offset null trim pin 2. Connect a potentiometer between OFFSET N1 (pin 1) and OFFSET N2 (pin 5) with the wiper tied to VCC- to trim the input offset voltage.
6 OUT output Op-amp output. Short-circuit protected with unlimited short-circuit duration. Typical peak swing +/-13.5 V into 10 kOhm on +/-15 V supplies; unity-gain bandwidth 3 MHz, slew rate 13 V/us typ.
7 VCC+ power_in Positive supply rail. Rated up to +18 V absolute maximum; typically operated at +15 V (dual supply) or the single-supply rail. Supply current 1.4 mA typ.
8 NC unconnected No internal connection. Leave floating or tie to any convenient net.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Op-amp/Cmp
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • TL071CDR
  • TL071CDRACD
  • TL071CDRACDR
  • TL071CDRBCD
  • TL071CDRBCDR
  • TL071CDRID
  • TL071CDRIDR
  • TL071CDRCP
  • TL071CDRACP
  • TL071CDRBCP
  • TL071CDRIP
  • TL071CDRCPSR

CAD (KiCad official)

  • Symbol: TL071CDR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tl071cdr-etched.step / tl071cdr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tl071cdr.step / tl071cdr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (36 pp, sha256 13558f1741483f56, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF