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TK100S04N1L

TOSHIBA · MOSFETs · DPAK

TK100S04N1L from TOSHIBA, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 Gate input Gate terminal; gate-source voltage limited to ±20 V with threshold Vth of 1.5 to 2.5 V (VDS = 10 V, ID = 0.5 mA).
2 Drain passive Drain terminal, connected to the heatsink tab; drain-source voltage rated 40 V and DC drain current 100 A.
3 Source passive Source terminal of the N-channel MOSFET; reverse drain current (DC) is 100 A max.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package DPAK
Category Triode/MOS Tube/Transistor
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-source voltage VDSS 40 V 2
Gate-source voltage VGSS -20 20 V 2
Drain current (DC) ID 100 A Tc = 25 2
Drain current (pulsed) IDP 200 A 2
Power dissipation PD 180 W Tc = 25 2
Single-pulse avalanche energy EAS 114 mJ VDD = 32 V, Tch = 25 (initial), L = 8.8 µH, RG = 1 Ω, IAS = 100 A 2
Single-pulse avalanche current IAS 100 A 2
Channel temperature Tch 175 °C 2
Storage temperature Tstg -55 175 °C 2
Channel-to-case thermal resistance Rth(ch-c) 0.83 /W 2
Gate leakage current IGSS -1 1 µA VGS = ±20 V, VDS = 0 V 3
Drain cut-off current IDSS 10 µA VDS = 40 V, VGS = 0 V 3
Drain-source breakdown voltage V(BR)DSS 40 V ID = 10 mA, VGS = 0 V 3
Drain-source breakdown voltage V(BR)DSX 20 V ID = 10 mA, VGS = -20 V 3
Gate threshold voltage Vth 1.5 2.5 V VDS = 10 V, ID = 0.5 mA 3
Drain-source on-resistance RDS(ON) 2.8 4.5 mΩ VGS = 4.5 V, ID = 50 A 3
Drain-source on-resistance RDS(ON) 1.9 2.3 mΩ VGS = 10 V, ID = 50 A 3
Reverse drain current (DC) IDR 100 A 3
Reverse drain current (pulsed) IDRP 200 A 3
Diode forward voltage VDSF -1.2 V IDR = 100 A, VGS = 0 V 3
Input capacitance Ciss 5490 pF VDS = 10 V, VGS = 0 V, f = 1 MHz 3
Reverse transfer capacitance Crss 220 pF VDS = 10 V, VGS = 0 V, f = 1 MHz 3
Output capacitance Coss 3000 pF VDS = 10 V, VGS = 0 V, f = 1 MHz 3
Switching time (rise time) tr 8 ns See Figure 6.2.1. 3
Switching time (turn-on time) ton 23 ns See Figure 6.2.1. 3
Switching time (fall time) tf 19 ns See Figure 6.2.1. 3
Switching time (turn-off time) toff 80 ns See Figure 6.2.1. 3
Total gate charge Qg 76 nC VDD ≈ 32 V, VGS = 10 V, ID = 100 A 3
Gate-source charge 1 Qgs1 18 nC VDD ≈ 32 V, VGS = 10 V, ID = 100 A 3
Gate-drain charge Qgd 11 nC VDD ≈ 32 V, VGS = 10 V, ID = 100 A 3
Reverse recovery time trr 90 ns IDR = 100 A, VGS = 0 V, -dIDR/dt = 50 A/µs 3
Reverse recovery charge Qrr 90 nC IDR = 100 A, VGS = 0 V, -dIDR/dt = 50 A/µs 3

CAD (KiCad official)

  • Symbol: TK100S04N1L
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: DPAK (KiCad packages3D, STEP)
  • 3D model files: tk100s04n1l-etched.step / tk100s04n1l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tk100s04n1l.step / tk100s04n1l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (9 pp, sha256 df7c8dcbf3bd96fe, retrieved 2026-10-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF