component
TJA1442AT
Public Made by Adomby adom
NXP Semicon CAN ICs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTJA1442AT
NXP Semicon · CAN ICs · SO-8
TJA1442AT from NXP Semicon, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | Transmit data input; inputs data from the CAN controller to be written to the bus lines. |
| 2 | GND | power_in | Ground. |
| 3 | VCC | power_in | 5 V supply voltage input (4.5 V to 5.5 V). |
| 4 | RXD | output | Receive data output; outputs data read from the bus lines to the CAN controller. |
| 5 | VIO | power_in | Supply voltage input for I/O level adapter in TJA1442A (2.95 V to 5.5 V). |
| 6 | CANL | bidirectional | LOW-level CAN bus line. |
| 7 | CANH | bidirectional | HIGH-level CAN bus line. |
| 8 | STB | input | Standby mode control input; active-HIGH. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | SO-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage | VCC | 4.5 | 5.5 | V | 14 | ||
| VIO supply voltage | VIO | 2.95 | 5.5 | V | TJA1442A | 14 | |
| Standby undervoltage detection voltage VCC | Vuvd(stb) | 4 | 4.5 | V | 14 | ||
| Standby undervoltage hysteresis voltage | Vuvhys(stb) | 50 | mV | 14 | |||
| VCC supply current, Normal mode dominant | ICC | 38 | 60 | mA | dominant; VTXD = 0 V; t < tto(dom)TXD | 14 | |
| VCC supply current, dominant short circuit | ICC | 125 | mA | dominant; VTXD = 0 V; short circuit on bus lines; -3 V < (VCANH = VCANL) < +40 V | 14 | ||
| VCC supply current, Normal mode recessive | ICC | 4 | 7 | mA | recessive; VTXD = VIO | 14 | |
| VCC supply current, Standby mode | ICC | 2 | µA | Standby mode; TJA1442A; Tvj < 85 °C | 14 | ||
| VIO switch-off undervoltage detection voltage | Vuvd(swoff) | 2.65 | 2.95 | V | pin VIO | 14 | |
| VIO supply current, Normal mode dominant | IIO | 250 | 760 | µA | Normal mode, dominant; VTXD = 0 V | 14 | |
| VIO supply current, Normal mode recessive | IIO | 150 | 460 | µA | Normal mode, recessive; VTXD = VIO | 14 | |
| VIO supply current, Standby mode | IIO | 8 | 11 | µA | Standby mode; Tvj < 85 °C | 15 | |
| TXD HIGH-level input voltage | VIH | 0.7 | V | 0.7VIO (min); pin TXD | 15 | ||
| TXD LOW-level input voltage | VIL | 0.3 | V | 0.3VIO (max); pin TXD | 15 | ||
| TXD hysteresis voltage | Vhys(TXD) | 50 | mV | 15 | |||
| TXD pull-up resistance | Rpu | 20 | 80 | kΩ | pin TXD | 15 | |
| TXD input capacitance | Ci | 10 | pF | pin TXD | 15 | ||
| RXD HIGH-level output current | IOH | -10 | -1 | mA | VRXD = VIO - 0.4 V | 15 | |
| RXD LOW-level output current | IOL | 1 | 10 | mA | VRXD = 0.4 V; bus dominant | 15 | |
| STB HIGH-level input voltage | VIH | 0.7 | V | 0.7VIO (min); pin STB | 15 | ||
| STB LOW-level input voltage | VIL | 0.3 | V | 0.3VIO (max); pin STB | 15 | ||
| STB hysteresis voltage | Vhys | 50 | mV | 15 | |||
| STB pull-up resistance | Rpu | 20 | 80 | kΩ | pin STB | 15 | |
| STB input capacitance | Ci | 10 | pF | pin STB | 15 | ||
| CANH dominant output voltage | VO(dom) | 2.75 | 3.5 | 4.5 | V | VTXD = 0 V; t < tto(dom)TXD; VCC ≥ 4.75 V; pin CANH; RL = 50 Ω to 65 Ω | 15 |
| CANL dominant output voltage | VO(dom) | 0.5 | 1.5 | 2.25 | V | VTXD = 0 V; t < tto(dom)TXD; VCC ≥ 4.75 V; pin CANL; RL = 50 Ω to 65 Ω | 15 |
| Transmitter voltage symmetry | VTXsym | 0.9 | 1.1 | V | VTXsym = VCANH + VCANL; CSPLIT = 4.7 nF; fTXD = 250 kHz, 1 MHz or 2.5 MHz; min/max as multiples of VCC (0.9VCC, 1.1VCC) | 15 | |
| Common mode voltage step | Vcm(step) | -150 | 150 | mV | 15 | ||
| Peak-to-peak common mode voltage | Vcm(p-p) | -300 | 300 | mV | 15 | ||
| Differential output voltage, dominant | VO(dif) | 1.5 | 3 | V | dominant; Normal mode; VTXD = 0 V; t < tto(dom)TXD; VCC ≥ 4.75 V; RL = 50 Ω to 65 Ω | 15 | |
| Differential output voltage, dominant | VO(dif) | 1.4 | 3.3 | V | dominant; Normal mode; VTXD = 0 V; t < tto(dom)TXD; VCC ≥ 4.75 V; RL = 45 Ω to 70 Ω | 15 | |
| Differential output voltage, dominant | VO(dif) | 1.5 | 5 | V | dominant; Normal mode; VTXD = 0 V; t < tto(dom)TXD; VCC ≥ 4.75 V; RL = 2240 Ω | 15 | |
| Differential output voltage, recessive | VO(dif) | -50 | 50 | mV | recessive; no load; Normal mode; VTXD = VIO | 15 | |
| Differential output voltage, recessive Standby | VO(dif) | -0.2 | 0.2 | V | Standby mode | 16 | |
| Recessive output voltage, Normal mode | VO(rec) | 2 | 2.5 | 3 | V | Normal mode; VTXD = VIO; no load | 16 |
| Recessive output voltage, Standby | VO(rec) | -0.1 | 0.1 | V | Standby mode; no load | 16 | |
| Differential receiver threshold voltage, Normal | Vth(RX)dif | 0.5 | 0.9 | V | -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V; Normal mode | 16 | |
| Differential receiver threshold voltage, Standby | Vth(RX)dif | 0.4 | 1.1 | V | -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V; Standby mode | 16 | |
| Receiver recessive voltage, Normal | Vrec(RX) | -4 | 0.5 | V | -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V; Normal mode | 16 | |
| Receiver recessive voltage, Standby | Vrec(RX) | -4 | 0.4 | V | -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V; Standby mode | 16 | |
| Receiver dominant voltage, Normal | Vdom(RX) | 0.9 | 9 | V | -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V; Normal mode | 16 | |
| Receiver dominant voltage, Standby | Vdom(RX) | 1.1 | 9 | V | -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V; Standby mode | 16 | |
| Differential receiver hysteresis voltage | Vhys(RX)dif | 50 | mV | -12 V ≤ VCANH ≤ +12 V; -12 V ≤ VCANL ≤ +12 V; Normal mode | 16 | ||
| Short-circuit output current | IO(sc) | 115 | mA | -15 V ≤ VCANH ≤ +40 V; -15 V ≤ VCANL ≤ +40 V | 16 | ||
| Recessive short-circuit output current | IO(sc)rec | -3 | 3 | mA | -27 V ≤ VCANH ≤ +32 V; -27 V ≤ VCANL ≤ +32 V; Normal mode; VTXD = VIO | 16 | |
| Leakage current | IL | -10 | 10 | µA | VCC = VIO = 0 V or pins shorted to GND via 47 KΩ; VCANH = VCANL = 5 V | 16 | |
| Input resistance | Ri | 25 | 40 | 50 | kΩ | -2 V ≤ VCANL ≤ +7 V; -2 V ≤ VCANH ≤ +7 V | 16 |
| Input resistance deviation | ΔRi | -3 | 3 | % | 0 V ≤ VCANL ≤ +5 V; 0 V ≤ VCANH ≤ +5 V | 16 | |
| Differential input resistance | Ri(dif) | 50 | 80 | 100 | kΩ | -2 V ≤ VCANL ≤ +7 V; -2 V ≤ VCANH ≤ +7 V | 16 |
| Common-mode input capacitance | Ci(cm) | 20 | pF | 16 | |||
| Differential input capacitance | Ci(dif) | 10 | pF | 16 | |||
| Shutdown junction temperature | Tj(sd) | 180 | 200 | °C | 16 | ||
| Release shutdown junction temperature | Tj(sd)rel | 175 | 195 | °C | 16 | ||
| Delay time TXD to bus dominant | td(TXD-busdom) | 102.5 | ns | Normal mode | 18 | ||
| Delay time TXD to bus recessive | td(TXD-busrec) | 102.5 | ns | Normal mode | 18 | ||
| Delay time bus dominant to RXD | td(busdom-RXD) | 115 | ns | Normal mode | 18 | ||
| Delay time bus recessive to RXD | td(busrec-RXD) | 115 | ns | Normal mode | 18 | ||
| Delay time TXD LOW to RXD LOW | td(TXDL-RXDL) | 215 | ns | Normal mode | 18 | ||
| Delay time TXD HIGH to RXD HIGH | td(TXDH-RXDH) | 215 | ns | Normal mode | 18 | ||
| Transmitted recessive bit width, 500 ns | tbit(bus) | 435 | 530 | ns | tbit(TXD) = 500 ns | 18 | |
| Transmitted recessive bit width, 200 ns | tbit(bus) | 155 | 210 | ns | tbit(TXD) = 200 ns | 18 | |
| Receiver timing symmetry, 500 ns | Δtrec | -65 | 40 | ns | tbit(TXD) = 500 ns | 18 | |
| Receiver timing symmetry, 200 ns | Δtrec | -45 | 15 | ns | tbit(TXD) = 200 ns | 18 | |
| Bit time on pin RXD, 500 ns | tbit(RXD) | 400 | 550 | ns | tbit(TXD) = 500 ns | 18 | |
| Bit time on pin RXD, 200 ns | tbit(RXD) | 120 | 220 | ns | tbit(TXD) = 200 ns | 18 | |
| Absolute max voltage on VCC, VIO, TXD, STB | Vx | -0.3 | 6 | V | pins VCC, VIO (TJA1442A), TXD, STB | 13 | |
| Absolute max voltage on CANH, CANL | Vx | -36 | 40 | V | pins CANH, CANL | 13 | |
| Virtual junction temperature | Tvj | -40 | 150 | °C | 13 | ||
| Thermal resistance junction to ambient | Rth(j-a) | 96 | K/W | SO8; free convection, JEDEC 2S2P board | 14 |
CAD (KiCad official)
- Symbol:
TJA1442AT - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SO-8 (KiCad packages3D, STEP)
- 3D model files:
tja1442at-etched.step/tja1442at-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tja1442at.step/tja1442at.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NXP Semicon datasheet (33 pp, sha256
174d600be47b04e5, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).