# TJA1057GTKZ

**NXP Semicon** · CAN ICs · HVSON-8-EP(3x3)

TJA1057GTKZ from NXP Semicon, in a HVSON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | Transmit data input; a LOW level drives the bus dominant, and an internal pull-up to VCC holds the pin HIGH if left floating. |
| 2 | GND | power_in | Ground; the GND pin must be soldered to board ground, and the exposed center pad is also recommended to be soldered to board ground. |
| 3 | VCC | power_in | Supply voltage for the transceiver. |
| 4 | RXD | output | Receive data output that reads out data from the bus lines. |
| 5 | n.c. | unconnected | Not connected in the TJA1057GTK variant (a VIO pin exists only in the TJA1057GTK/3 and TJA1057BTK variants). |
| 6 | CANL | bidirectional | LOW-level CAN bus line (analog input/output). |
| 7 | CANH | bidirectional | HIGH-level CAN bus line (analog input/output). |
| 8 | S | input | Silent mode control input; a LOW level selects Normal mode and a HIGH level selects Silent mode. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | HVSON-8-EP(3x3) |
| Category | Interface ICs |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| voltage on pin x (CANH, CANL) | Vx | -42 |  | 42 | V | on pins CANH, CANL | 8 |
| voltage on pin x (VCC, VIO) | Vx | -0.3 |  | 7 | V | on pins VCC, VIO | 8 |
| voltage on pin x (any other pin) | Vx | -0.3 |  |  | V | on any other pin | 8 |
| voltage between pin CANH and pin CANL | V(CANH-CANL) | -27 |  | 27 | V |  | 8 |
| transient voltage pulse 1 | Vtrt | -100 |  |  | V | on pins CANH, CANL; pulse 1 | 8 |
| transient voltage pulse 2a | Vtrt |  |  | 75 | V | on pins CANH, CANL; pulse 2a | 8 |
| transient voltage pulse 3a | Vtrt | -150 |  |  | V | on pins CANH, CANL; pulse 3a | 8 |
| electrostatic discharge voltage (IEC 61000-4-2) | VESD | -8 |  | 8 | kV | IEC 61000-4-2 (150 pF, 330 Ω discharge circuit); on pins CANH and CANL | 8 |
| electrostatic discharge voltage (SAE J2962-2 powered air discharge) | VESD | -15 |  | 15 | kV | SAE J2962-2:2019 (330 pF, 2kΩ) on pins CANH, CANL; powered air discharge | 8 |
| electrostatic discharge voltage (HBM) | VESD | -4 |  | 4 | kV | Human Body Model (HBM); on any pin | 8 |
| electrostatic discharge voltage (CDM) | VESD | -750 |  | 750 | V | Charged Device Model (CDM); on corner pins | 8 |
| virtual junction temperature | Tvj | -40 |  | 150 | °C |  | 8 |
| storage temperature | Tstg | -55 |  | 150 | °C |  | 8 |
| supply voltage on pin VCC | VCC | 4.5 |  | 5.5 | V |  | 9 |
| undervoltage detection voltage on pin VCC | Vuvd(VCC) | 3.5 | 4 | 4.3 | V |  | 9 |
| supply current in silent mode | ICC | 0.1 |  | 1.2 | mA | Silent mode; VTXD = VIO | 9 |
| supply current in normal mode, recessive | ICC | 2 | 5 | 10 | mA | Normal mode; recessive; VTXD = VIO | 9 |
| supply current in normal mode, dominant | ICC | 20 | 45 | 70 | mA | Normal mode; dominant; VTXD = 0 V | 9 |
| supply current, dominant with short circuit on bus lines | ICC | 2 | 80 | 110 | mA | dominant; short circuit on bus lines; VTXD = 0 V; -3 V < (VCANH = VCANL) < +18 V | 9 |
| HIGH-level input voltage, pin S | VIH | 2 |  |  | V | pin S | 10 |
| LOW-level input voltage, pin S | VIL | -0.3 |  | 0.8 | V | pin S | 10 |
| HIGH-level input voltage, pin TXD | VIH | 2 |  |  | V | pin TXD | 10 |
| LOW-level input voltage, pin TXD | VIL | -0.3 |  | 0.8 | V | pin TXD | 10 |
| LOW-level input current, pin TXD | IIL | -260 |  | -30 | μA | VTXD = 0 V | 10 |
| HIGH-level output current, pin RXD | IOH | -9 | -3 | -1 | mA | VRXD = VIO - 0.4 V | 10 |
| LOW-level output current, pin RXD | IOL | 1 |  | 12 | mA | VRXD = 0.4 V; bus dominant | 10 |
| dominant output voltage, pin CANH | VO(dom) | 2.75 | 3.5 | 4.5 | V | VTXD = 0 V; t < tto(dom)TXD; pin CANH; RL = 50 Ω to 65 Ω | 10 |
| dominant output voltage, pin CANL | VO(dom) | 0.5 | 1.5 | 2.25 | V | VTXD = 0 V; t < tto(dom)TXD; pin CANL; RL = 50 Ω to 65 Ω | 10 |
| transmitter dominant voltage symmetry | Vdom(TX)sym | -400 |  | 400 | mV | Vdom(TX)sym = VCC - VCANH - VCANL | 10 |
| differential dominant output voltage | VO(dif) | 1.5 |  | 3 | V | dominant; VTXD = 0 V; t < tto(dom)TXD; RL = 50 to 65 Ω | 10 |
| differential dominant output voltage | VO(dif) | 1.5 |  | 5 | V | dominant; VTXD = 0 V; t < tto(dom)TXD; RL = 2240 Ω | 10 |
| differential recessive output voltage | VO(dif) | -50 |  | 50 | mV | recessive; VTXD = VIO; no load | 10 |
| recessive output voltage | VO(rec) | 2 |  | 3 | V | VTXD = VIO; no load | 10 |
| differential receiver threshold voltage | Vth(RX)dif | 0.5 |  | 0.9 | V | Normal/Silent mode; -12 V ≤ VCANL ≤ +12 V; -12 V ≤ VCANH ≤ +12 V | 10 |
| receiver recessive voltage | Vrec(RX) | -4 |  | 0.5 | V | Normal/Silent mode; -12 V ≤ VCANL ≤ +12 V; -12 V ≤ VCANH ≤ +12 V | 10 |
| receiver dominant voltage | Vdom(RX) | 0.9 |  | 9 | V | Normal/Silent mode; -12 V ≤ VCANL ≤ +12 V; -12 V ≤ VCANH ≤ +12 V | 10 |
| differential receiver hysteresis voltage | Vhys(RX)dif | 50 |  | 300 | mV | Normal mode; -12 V ≤ VCANL ≤ +12 V; -12 V ≤ VCANH ≤ +12 V | 11 |
| dominant short-circuit output current, pin CANH | IO(sc)dom | -100 | -70 |  | mA | VTXD = 0 V; t < tto(dom)TXD; VCC = 5 V; pin CANH; VCANH = -15 V to +40 V | 11 |
| dominant short-circuit output current, pin CANL | IO(sc)dom |  | 70 | 100 | mA | VTXD = 0 V; t < tto(dom)TXD; VCC = 5 V; pin CANL; VCANL = -15 V to +40 V | 11 |
| recessive short-circuit output current | IO(sc)rec | -5 |  | 5 | mA | Normal mode; VTXD = VCC; VCANH = VCANL = -27 V to +32 V | 11 |
| leakage current on pins CANH, CANL | IL | -5 |  | 5 | μA | VCC = 0 V or VCC = VIO = shorted to ground via 47 kΩ; VCANH = VCANL = 5 V | 11 |
| input resistance | Ri | 9 | 15 | 28 | kΩ | -2 V ≤ VCANL ≤ +7 V; -2 V ≤ VCANH ≤ +7 V | 11 |
| differential input resistance | Ri(dif) | 19 | 30 | 52 | kΩ | -2 V ≤ VCANL ≤ +7 V; -2 V ≤ VCANH ≤ +7 V | 11 |
| transceiver delay time from TXD to bus dominant (other variants) | td(TXD-busdom) |  | 65 | 105 | ns | other variants; Normal mode | 12 |
| transceiver delay time from TXD to bus recessive (other variants) | td(TXD-busrec) |  | 90 | 105 | ns | other variants; Normal mode | 12 |
| transceiver delay time from bus dominant to RXD (other variants) | td(busdom-RXD) |  | 60 | 115 | ns | other variants; Normal mode | 12 |
| transceiver delay time from bus recessive to RXD (other variants) | td(busrec-RXD) |  | 65 | 135 | ns | other variants; Normal mode | 12 |
| loop delay from TXD LOW to RXD LOW (other variants) | td(TXDL-RXDL) | 50 |  | 230 | ns | other variants; Normal mode | 12 |
| loop delay from TXD LOW to RXD LOW (other variants, VCC 4.75 V to 5.25 V) | td(TXDL-RXDL) | 50 |  | 210 | ns | other variants; Normal mode; VCC = 4.75 V to 5.25 V | 12 |
| loop delay from TXD HIGH to RXD HIGH (other variants) | td(TXDH-RXDH) | 50 |  | 230 | ns | other variants; Normal mode | 12 |
| loop delay from TXD HIGH to RXD HIGH (other variants, VCC 4.75 V to 5.25 V) | td(TXDH-RXDH) | 50 |  | 210 | ns | other variants; Normal mode; VCC = 4.75 V to 5.25 V | 12 |
| transmitted recessive bit width deviation, parameter set B | Δtbit(bus) | -45 |  | 10 | ns | parameter set B (tbit(TXD) ≥ 200 ns, up to 5 Mbit/s); Δtbit(bus) = tbit(bus) - tbit(TXD) | 12 |
| received recessive bit width deviation, parameter set B | Δtbit(RXD) | -80 |  | 20 | ns | parameter set B (tbit(TXD) ≥ 200 ns, up to 5 Mbit/s); Δtbit(RXD) = tbit(RXD) - tbit(TXD) | 12 |
| receiver timing symmetry, parameter set B | Δtrec | -45 |  | 15 | ns | parameter set B (tbit(TXD) ≥ 200 ns, up to 5 Mbit/s); Δtrec = tbit(RXD) - tbit(bus) | 12 |
| transmitted recessive bit width deviation, parameter set A | Δtbit(bus) | -65 |  | 30 | ns | parameter set A (tbit(TXD) ≥ 500 ns, up to 2 Mbit/s); Δtbit(bus) = tbit(bus) - tbit(TXD) | 12 |
| received recessive bit width deviation, parameter set A | Δtbit(RXD) | -100 |  | 50 | ns | parameter set A (tbit(TXD) ≥ 500 ns, up to 2 Mbit/s); Δtbit(RXD) = tbit(RXD) - tbit(TXD) | 12 |
| receiver timing symmetry, parameter set A | Δtrec | -65 |  | 40 | ns | parameter set A (tbit(TXD) ≥ 500 ns, up to 2 Mbit/s); Δtrec = tbit(RXD) - tbit(bus) | 12 |
| TXD dominant time-out time | tto(dom)TXD | 0.8 | 3 | 6.5 | ms | VTXD = 0 V; Normal mode | 12 |
| thermal resistance from junction to ambient (HVSON8) | Rth(j-a) |  | 54 |  | K/W | HVSON8 package; in free air | 9 |
| thermal resistance from junction to case (HVSON8) | Rth(j-c) |  | 16 |  | K/W | HVSON8 package; in free air | 9 |

## CAD (KiCad official)

- Symbol: `TJA1057GTKZ`
- Footprint: `Package_SON:HVSON-8-1EP_3x3mm_P0.65mm_EP1.6x2.4mm`
- 3D model: HVSON-8-EP(3x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal VQFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `tja1057gtkz-etched.step` / `tja1057gtkz-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tja1057gtkz.step` / `tja1057gtkz.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [NXP Semicon datasheet](https://www.nxp.com/docs/en/data-sheet/TJA1057.pdf) (26 pp, sha256 `65a502b18c2f52f7`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tja1057gtkz-datasheet.pdf)