TJA1050DRG

{
  "schema_version": 1,
  "type": "component",
  "slug": "tja1050drg",
  "title": "TJA1050DRG",
  "brief": "HANSCHIP semiconductor CAN ICs, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "comm-uart",
    "tja1050drg"
  ],
  "component": {
    "mpn": "TJA1050DRG",
    "manufacturer": "HANSCHIP semiconductor",
    "package": "SOP-8",
    "pin_count": 8,
    "category": "Comm/UART",
    "subcategory": "CAN ICs",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312291742_HANSCHIP-semiconductor-TJA1050DRG_C19723770.pdf",
    "parts": {
      "symbol": "tja1050drg.kicad_sym",
      "footprint": "tja1050drg.kicad_mod",
      "model_3d": "tja1050drg-etched.glb",
      "model_3d_plain": "tja1050drg.glb",
      "model_3d_step": "tja1050drg-etched.step",
      "model_3d_step_plain": "tja1050drg.step",
      "lbr": "tja1050drg.lbr"
    },
    "distributor_links": {
      "lcsc": "C19723770"
    },
    "pins": [
      {
        "number": "1",
        "name": "TXD",
        "type": "input",
        "description": "Transmit data input from the CAN controller. TTL/CMOS-compatible input (VIH ≥ 2 V, VIL ≤ 0.8 V, tolerant to VCC+0.3 V). Driving low forces a dominant bit on the bus; high (or floating with internal pull-up) leaves the bus recessive."
      },
      {
        "number": "2",
        "name": "GND",
        "type": "power_in",
        "description": "Device ground reference. Connect to the system 0 V rail."
      },
      {
        "number": "3",
        "name": "VCC",
        "type": "power_in",
        "description": "Supply voltage input, 4.75 V to 5.25 V nominal (absolute max −0.3 V to 6 V). Typical ICC ≈ 5 mA recessive / 50 mA dominant in normal mode and ≈10 µA in standby mode. Decouple locally with a 100 nF ceramic capacitor."
      },
      {
        "number": "4",
        "name": "RXD",
        "type": "output",
        "description": "Receive data output to the CAN controller. Reports the bus state: LOW = dominant, HIGH = recessive. Push-pull output with VOH ≈ VCC−0.7 V at −100 µA and IOL sink capability of 6 mA typ."
      },
      {
        "number": "5",
        "name": "SPLIT",
        "type": "output",
        "description": "Common-mode stabilization output, typically 0.5·VCC in normal mode (driving up to ±500 µA). Intended for connection to the mid-point of a split bus termination (two 60 Ω resistors) to improve EMC. High-impedance in standby mode; ±27 V DC tolerant."
      },
      {
        "number": "6",
        "name": "CANL",
        "type": "bidirectional",
        "description": "Low-side CAN bus line. Dominant output ≈1.4 V (0.5-1.75 V); recessive ≈0.5·VCC. Withstands −27 V to +40 V DC and ISO 7637 transients to ±200 V; ESD ±6 kV HBM."
      },
      {
        "number": "7",
        "name": "CANH",
        "type": "bidirectional",
        "description": "High-side CAN bus line. Dominant output ≈3.6 V (3.0-4.25 V); recessive ≈0.5·VCC. Withstands −27 V to +40 V DC and ISO 7637 transients to ±200 V; ESD ±6 kV HBM."
      },
      {
        "number": "8",
        "name": "STB",
        "type": "input",
        "description": "Standby-mode control input. LOW = normal (high-speed) mode; HIGH = low-current standby with bus wake-up detection. TTL/CMOS-compatible (VIH ≥ 2 V, VIL ≤ 0.8 V)."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2312291742_HANSCHIP-semiconductor-TJA1050DRG_C19723770.pdf",
        "pages": 11,
        "sha256": "510a842962d0cdd8",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -1.905
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
      "mark": "drawn"
    },
    "models_3d": [
      {
        "file": "tja1050drg.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "tja1050drg-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6.0,
          4.9,
          1.75
        ],
        "zmin_mm": -0.0,
        "centre_offset_mm": 0.0,
        "footprint_binding": "identity",
        "sha256": "bd20899bd63f126a05e4f680ee5b8747ebeca7edd3e10558731a165797b3cca0",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "HANSCHIP semiconductor",
      "Package": "SOP-8",
      "Category": "Comm/UART",
      "Pins": "8"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "tja1050drg"
  ],
  "discovery_pitch": "TJA1050DRG (HANSCHIP semiconductor) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray",
    "email": "[email protected]"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "tja1050drg.kicad_sym",
    "tja1050drg.kicad_mod",
    "tja1050drg.glb",
    "tja1050drg.step",
    "tja1050drg-etched.step",
    "tja1050drg.lbr",
    "docs/hero.png",
    "docs/tja1050drg-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "TJA1050DRG",
      "kind": "packaging"
    },
    {
      "mpn": "TJA1050DRGDGKRG",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-25T09:42:00.894Z"
}