component
TJA1042
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NXP high-speed CAN transceiver, SOIC-8. ISO 11898-2, up to 5 Mbps CAN FD, standby mode, VIO variant. Datasheet-verified.
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README.mdadded+52@@ -0,0 +1,52 @@+# TJA1042++**NXP** · CAN transceiver · SOIC-8++Physical-layer transceiver between a CAN or CAN FD controller and the bus, meeting ISO 11898-2 at data rates up to 5 Mbps. TXD and RXD face the controller, CANH and CANL the bus, and an STB pin selects normal or a low-power standby with bus-wakeup. The SPLIT pin stabilizes the bus common mode, and a VIO variant matches the logic side to 3.3 or 5 V controllers. Bus pins tolerate wide common-mode and high ESD for automotive wiring. A standard modern CAN FD transceiver.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | TXD | input | Transmit data input from the host controller. Internal pull-up to VIO (or VCC on non-VIO variants) drives the bus recessive when left floating. A TXD dominant time-out (t_to(dom)TXD) releases the bus if TXD is held LOW too long, which also sets the minimum bit rate of 40 kbit/s. |+| 2 | GND | power_in | Ground supply. On the HVSON8 package this pin is internally connected to the exposed center pad; the GND pin must be soldered to board ground and the pad is recommended for thermal/electrical performance. |+| 3 | VCC | power_in | Main transceiver supply voltage. Operating range 4.5 V to 5.5 V (absolute max -0.3 V to +7 V). Undervoltage detection (V_uvd(VCC) = 3.5-4.5 V) forces the device into Standby. |+| 4 | RXD | output | Receive data output; reads the digitized differential state of the CAN bus (LOW = dominant, HIGH = recessive). Also signals wake-up requests in Standby mode by going LOW after a valid filtered bus wake-up pattern. |+| 5 | SPLIT/VIO | bidirectional | Dual-function pin whose role depends on the ordering variant. On TJA1042T and TJA1042CT this is the SPLIT common-mode stabilization output that delivers 0.5*VCC in Normal mode (floating in Standby / VCC off) for splitting bus termination. On TJA1042T(K)/3 and TJA1042BT(K) this is the VIO supply input (2.8 V to 5.5 V) that sets the I/O level of TXD, RXD and STB and powers the low-power differential receiver for standalone bus wake-up. |+| 6 | CANL | bidirectional | LOW-level CAN bus line. Driven LOW (toward GND) in the dominant state and biased to ~0.5*VCC in recessive. High-voltage solid (-58 V to +58 V DC) and ±8 kV IEC 61000-4-2 ESD on the bus pin. |+| 7 | CANH | bidirectional | HIGH-level CAN bus line. Driven HIGH (toward VCC) in the dominant state and biased to ~0.5*VCC in recessive. High-voltage solid (-58 V to +58 V DC) and ±8 kV IEC 61000-4-2 ESD on the bus pin. |+| 8 | STB | input | Standby mode control input. LOW selects Normal mode (transmit/receive enabled); HIGH selects low-current Standby mode with bus wake-up via the low-power differential receiver. Internal pull-up to VIO (or VCC on non-VIO variants) defaults the device to Standby if left floating. |++## Key specifications++| Parameter | Value |+|---|---|+| Type | High-speed CAN / CAN FD transceiver |+| Standard | ISO 11898-2:2016 |+| Data rate | Up to 5 Mbps (CAN FD) |+| Supply | 5 V (VIO option for 3.3/5 V logic) |+| Modes | Normal / standby (STB) |+| Bus ESD | +/-8 kV (HBM) |+| Package | SOIC-8 |++## Ordering variants++- `TJA1042T (SOIC-8, no VIO)`+- `TJA1042T/3 (SOIC-8, with VIO)`+- `TJA1042TK/3 (SOIC-8, HVSON)`++## CAD (KiCad official)++- Symbol: `Interface_CAN_LIN:TJA1042T (KiCad official)`+- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`+- 3D model: SOIC-8 (KiCad packages3D, STEP)++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [NXP datasheet](https://www.nxp.com/docs/en/data-sheet/TJA1042.pdf) (27 pp, sha256 `aac9491f00e59436`, retrieved 2026-08-17, tier: manufacturer)+- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/tja1042-datasheet.pdf)
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