component
TJA1041T
Public Made by Adomby adom
NXP Semicon CAN ICs, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TJA1041T
NXP Semicon · CAN ICs · SOIC-14
TJA1041T from NXP Semicon, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | Transmit data input (Table 3); the datasheet gives no further limits for this pin in the pin description. |
| 2 | GND | power_in | Ground connection (Table 3). |
| 3 | VCC | power_in | Transceiver supply voltage input; the operating range is 4.75 V to 5.25 V per the quick reference data (Table 1, page 2). |
| 4 | RXD | output | Receive data output that reads out data from the bus lines (Table 3). |
| 5 | VI/O | power_in | I/O-level adapter voltage input, operating range 2.8 V to 5.25 V per the quick reference data (Table 1, page 2), which sets the I/O levels to the host controller supply. |
| 6 | EN | input | Enable control input; together with STB it selects the operating mode (Table 3, Table 4). |
| 7 | INH | output | Inhibit output for switching external voltage regulators (Table 3); per Table 4 it is H in Standby mode and floating in Sleep mode. |
| 8 | ERR | output | Error and power-on indication output, active LOW (Table 3). |
| 9 | WAKE | input | Local wake-up input (Table 3). |
| 10 | VBAT | power_in | Battery voltage input; operating range 5 V to 27 V per the quick reference data (Table 1, page 2). |
| 11 | SPLIT | output | Common-mode stabilization output (Table 3). |
| 12 | CANL | bidirectional | LOW-level CAN bus line (Table 3); DC voltage limit −27 V to +40 V with 0 V < VCC < 5.25 V and no time limit (Table 1, page 2). |
| 13 | CANH | bidirectional | HIGH-level CAN bus line (Table 3); DC voltage limit −27 V to +40 V with 0 V < VCC < 5.25 V and no time limit (Table 1, page 2). |
| 14 | STB | input | Standby control input, active LOW (Table 3); together with EN it selects the operating mode (Table 4). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | SOIC-14 |
| Category | Interface ICs |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC voltage on pin VCC operating range | VCC | 4.75 | 5.25 | V | operating range | 11 | |
| DC voltage on pin VI/O operating range | VI/O | 2.8 | 5.25 | V | operating range | 11 | |
| DC voltage on pin VBAT operating range | VBAT | 5 | 27 | V | operating range | 11 | |
| DC voltage on pin VCC | VCC | -0.3 | 6 | V | no time limit | 11 | |
| DC voltage on pin VI/O | VI/O | -0.3 | 6 | V | no time limit | 11 | |
| DC voltage on pin VBAT | VBAT | -0.3 | 40 | V | no time limit | 11 | |
| load dump on pin VBAT | VBAT | 40 | V | 11 | |||
| DC current on pin WAKE | IWAKE | -15 | mA | 11 | |||
| DC voltage on pin CANH | VCANH | -27 | 40 | V | 0 V < VCC < 5.25 V; no time limit | 11 | |
| DC voltage on pin CANL | VCANL | -27 | 40 | V | 0 V < VCC < 5.25 V; no time limit | 11 | |
| DC voltage on pin SPLIT | VSPLIT | -27 | 40 | V | 0 V < VCC < 5.25 V; no time limit | 11 | |
| transient voltages on pins CANH, CANL, SPLIT and VBAT | Vtrt | -200 | 200 | V | according to ISO 7637; see Figure 6 | 11 | |
| electrostatic discharge voltage HBM, pins CANH, CANL and SPLIT | Vesd | -6 | 6 | kV | Human Body Model (HBM) | 11 | |
| electrostatic discharge voltage HBM, pins TXD, RXD, VI/O and STB | Vesd | -3 | 3 | kV | Human Body Model (HBM) | 11 | |
| electrostatic discharge voltage HBM, all other pins | Vesd | -4 | 4 | kV | Human Body Model (HBM) | 11 | |
| electrostatic discharge voltage Machine Model | Vesd | -200 | 200 | V | Machine Model (MM) | 11 | |
| virtual junction temperature | Tvj | -40 | 150 | °C | 11 | ||
| storage temperature | Tstg | -55 | 150 | °C | 11 | ||
| VCC undervoltage detection level for forced Sleep mode | VCC(sleep) | 2.75 | 3.3 | 4.5 | V | VBAT = 12 V (fail-safe) | 12 |
| VI/O undervoltage detection level for forced Sleep mode | VI/O(sleep) | 0.5 | 1.5 | 2 | V | 12 | |
| VBAT voltage level for fail-safe fallback mode | VBAT(stb) | 2.75 | 3.3 | 4.5 | V | VCC = 5 V (fail-safe) | 12 |
| VBAT voltage level for setting pwon flag | VBAT(pwon) | 2.5 | 3.3 | 4.1 | V | VCC = 0 V | 12 |
| VCC input current, dominant | ICC | 25 | 55 | 80 | mA | normal mode; VTXD = 0 V (dominant) | 12 |
| VCC input current, recessive | ICC | 2 | 6 | 10 | mA | normal or pwon/listen-only mode; VTXD = VI/O (recessive) | 12 |
| VI/O input current, dominant | II/O | 100 | 350 | 1000 | µA | normal mode; VTXD = 0 V (dominant) | 12 |
| VI/O input current, recessive | II/O | 15 | 80 | 200 | µA | normal or pwon/listen-only mode; VTXD = VI/O (recessive) | 12 |
| VBAT input current, normal mode | IBAT | 15 | 30 | 40 | µA | normal or pwon/listen-only mode | 12 |
| VBAT input current, Standby mode | IBAT | 10 | 20 | 30 | µA | Standby mode; VCC > 4.75 V; VI/O = 2.8 V; VINH = VWAKE = VBAT = 12 V | 12 |
| VBAT input current, Sleep mode | IBAT | 10 | 20 | 30 | µA | Sleep mode; VINH = VCC = VI/O = 0 V; VWAKE = VBAT = 12 V | 12 |
| LOW-level input voltage pin TXD | VIL | -0.3 | V | max printed as +0.3VI/O | 12 | ||
| HIGH-level input current pin TXD | IIH | -5 | 0 | 5 | µA | normal or pwon/listen-only mode; VTXD = VI/O | 12 |
| LOW-level input current pin TXD | IIL | -70 | -250 | -500 | µA | normal or pwon/listen-only mode; VTXD = 0.3VI/O | 13 |
| HIGH-level output current pin RXD | IOH | -1 | -3 | -6 | mA | VRXD = VI/O − 0.4 V; VI/O = VCC | 13 |
| LOW-level output current pin RXD | IOL | 2 | 5 | 12 | mA | VRXD = 0.4 V; VTXD = VI/O; bus dominant | 13 |
| LOW-level input voltage pins STB and EN | VIL | -0.3 | V | max printed as +0.3VI/O | 13 | ||
| HIGH-level input current pins STB and EN | IIH | 1 | 4 | 10 | µA | VSTB = VEN = 0.7VI/O | 13 |
| HIGH-level output current pin ERR | IOH | -4 | -20 | -50 | µA | VERR = VI/O − 0.4 V; VI/O = VCC | 13 |
| LOW-level output current pin ERR | IOL | 0.1 | 0.2 | 0.35 | mA | VERR = 0.4 V | 13 |
| HIGH-level input current pin WAKE | IIH | -1 | -5 | -10 | µA | VWAKE = VBAT − 1.9 V | 13 |
| LOW-level input current pin WAKE | IIL | 1 | 5 | 10 | µA | VWAKE = VBAT − 3.1 V | 13 |
| dominant output voltage pin CANH | VO(dom) | 3 | 3.6 | 4.25 | V | VTXD = 0 V | 13 |
| dominant output voltage pin CANL | VO(dom) | 0.5 | 1.4 | 1.75 | V | VTXD = 0 V | 13 |
| differential bus output voltage (VCANH - VCANL), dominant | VO(dif)(bus) | 1.5 | 3 | V | VTXD = 0 V (dominant); 45 Ω < RL < 65 Ω | 13 | |
| recessive output voltage | VO(reces) | 2 | 3 | V | normal or pwon/listen-only mode; VTXD = VI/O; no load; typ printed as 0.5VCC | 13 | |
| short-circuit output current pin CANH | IO(sc) | -45 | -70 | -95 | mA | VTXD = 0 V (dominant); VCANH = 0 V | 13 |
| short-circuit output current pin CANL | IO(sc) | 45 | 70 | 95 | mA | VTXD = 0 V (dominant); VCANL = 40 V | 13 |
| differential receiver threshold voltage, normal mode | Vdif(th) | 0.5 | 0.7 | 0.9 | V | normal or pwon/listen-only mode; see Figure 7; −12 V < VCANH < 12 V; −12 V < VCANL < 12 V | 14 |
| differential receiver threshold voltage, Standby or Sleep mode | Vdif(th) | 0.4 | 0.7 | 1.15 | V | Standby or Sleep mode; −12 V < VCANH < 12 V; −12 V < VCANL < 12 V | 14 |
| differential receiver hysteresis voltage | Vhys(dif) | 50 | 70 | 100 | mV | normal or pwon/listen-only mode; see Figure 7; −12 V < VCANH < 12 V; −12 V < VCANL < 12 V | 14 |
| differential input resistance | Ri(dif) | 25 | 50 | 75 | kΩ | 14 | |
| common-mode input resistance | Ri(cm) | 15 | 25 | 35 | kΩ | 14 | |
| common-mode input capacitance | Ci(cm) | 20 | pF | VTXD = VCC; not tested | 14 | ||
| shutdown junction temperature | Tj(sd) | 155 | 165 | 180 | °C | 15 | |
| delay TXD to bus active | td(TXD-BUSon) | 25 | 70 | 110 | ns | normal mode | 14 |
| delay TXD to bus inactive | td(TXD-BUSoff) | 10 | 50 | 95 | ns | normal mode | 14 |
| delay bus active to RXD | td(BUSon-RXD) | 15 | 65 | 115 | ns | normal or pwon/listen-only mode | 14 |
| delay bus inactive to RXD | td(BUSoff-RXD) | 35 | 100 | 160 | ns | normal or pwon/listen-only mode | 14 |
| propagation delay TXD to RXD | tPD(TXD-RXD) | 40 | 255 | ns | VSTB = 0 V | 14 | |
| TXD dominant time-out | tdom(TXD) | 300 | 600 | 1000 | µs | VTXD = 0 V | 14 |
| thermal resistance from junction to ambient | Rth(j-a) | 120 | K/W | SO14 package; in free air | 12 |
CAD (KiCad official)
- Symbol:
TJA1041T - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files:
tja1041t-etched.step/tja1041t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tja1041t.step/tja1041t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NXP Semicon datasheet (26 pp, sha256
7c89e2ddf157a0e3, retrieved 2026-10-29, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TJA1041T
**NXP Semicon** · CAN ICs · SOIC-14
TJA1041T from NXP Semicon, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | Transmit data input (Table 3); the datasheet gives no further limits for this pin in the pin description. |
| 2 | GND | power_in | Ground connection (Table 3). |
| 3 | VCC | power_in | Transceiver supply voltage input; the operating range is 4.75 V to 5.25 V per the quick reference data (Table 1, page 2). |
| 4 | RXD | output | Receive data output that reads out data from the bus lines (Table 3). |
| 5 | VI/O | power_in | I/O-level adapter voltage input, operating range 2.8 V to 5.25 V per the quick reference data (Table 1, page 2), which sets the I/O levels to the host controller supply. |
| 6 | EN | input | Enable control input; together with STB it selects the operating mode (Table 3, Table 4). |
| 7 | INH | output | Inhibit output for switching external voltage regulators (Table 3); per Table 4 it is H in Standby mode and floating in Sleep mode. |
| 8 | ERR | output | Error and power-on indication output, active LOW (Table 3). |
| 9 | WAKE | input | Local wake-up input (Table 3). |
| 10 | VBAT | power_in | Battery voltage input; operating range 5 V to 27 V per the quick reference data (Table 1, page 2). |
| 11 | SPLIT | output | Common-mode stabilization output (Table 3). |
| 12 | CANL | bidirectional | LOW-level CAN bus line (Table 3); DC voltage limit −27 V to +40 V with 0 V < VCC < 5.25 V and no time limit (Table 1, page 2). |
| 13 | CANH | bidirectional | HIGH-level CAN bus line (Table 3); DC voltage limit −27 V to +40 V with 0 V < VCC < 5.25 V and no time limit (Table 1, page 2). |
| 14 | STB | input | Standby control input, active LOW (Table 3); together with EN it selects the operating mode (Table 4). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | SOIC-14 |
| Category | Interface ICs |
| Pins | 14 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC voltage on pin VCC operating range | VCC | 4.75 | | 5.25 | V | operating range | 11 |
| DC voltage on pin VI/O operating range | VI/O | 2.8 | | 5.25 | V | operating range | 11 |
| DC voltage on pin VBAT operating range | VBAT | 5 | | 27 | V | operating range | 11 |
| DC voltage on pin VCC | VCC | -0.3 | | 6 | V | no time limit | 11 |
| DC voltage on pin VI/O | VI/O | -0.3 | | 6 | V | no time limit | 11 |
| DC voltage on pin VBAT | VBAT | -0.3 | | 40 | V | no time limit | 11 |
| load dump on pin VBAT | VBAT | | | 40 | V | | 11 |
| DC current on pin WAKE | IWAKE | | | -15 | mA | | 11 |
| DC voltage on pin CANH | VCANH | -27 | | 40 | V | 0 V < VCC < 5.25 V; no time limit | 11 |
| DC voltage on pin CANL | VCANL | -27 | | 40 | V | 0 V < VCC < 5.25 V; no time limit | 11 |
| DC voltage on pin SPLIT | VSPLIT | -27 | | 40 | V | 0 V < VCC < 5.25 V; no time limit | 11 |
| transient voltages on pins CANH, CANL, SPLIT and VBAT | Vtrt | -200 | | 200 | V | according to ISO 7637; see Figure 6 | 11 |
| electrostatic discharge voltage HBM, pins CANH, CANL and SPLIT | Vesd | -6 | | 6 | kV | Human Body Model (HBM) | 11 |
| electrostatic discharge voltage HBM, pins TXD, RXD, VI/O and STB | Vesd | -3 | | 3 | kV | Human Body Model (HBM) | 11 |
| electrostatic discharge voltage HBM, all other pins | Vesd | -4 | | 4 | kV | Human Body Model (HBM) | 11 |
| electrostatic discharge voltage Machine Model | Vesd | -200 | | 200 | V | Machine Model (MM) | 11 |
| virtual junction temperature | Tvj | -40 | | 150 | °C | | 11 |
| storage temperature | Tstg | -55 | | 150 | °C | | 11 |
| VCC undervoltage detection level for forced Sleep mode | VCC(sleep) | 2.75 | 3.3 | 4.5 | V | VBAT = 12 V (fail-safe) | 12 |
| VI/O undervoltage detection level for forced Sleep mode | VI/O(sleep) | 0.5 | 1.5 | 2 | V | | 12 |
| VBAT voltage level for fail-safe fallback mode | VBAT(stb) | 2.75 | 3.3 | 4.5 | V | VCC = 5 V (fail-safe) | 12 |
| VBAT voltage level for setting pwon flag | VBAT(pwon) | 2.5 | 3.3 | 4.1 | V | VCC = 0 V | 12 |
| VCC input current, dominant | ICC | 25 | 55 | 80 | mA | normal mode; VTXD = 0 V (dominant) | 12 |
| VCC input current, recessive | ICC | 2 | 6 | 10 | mA | normal or pwon/listen-only mode; VTXD = VI/O (recessive) | 12 |
| VI/O input current, dominant | II/O | 100 | 350 | 1000 | µA | normal mode; VTXD = 0 V (dominant) | 12 |
| VI/O input current, recessive | II/O | 15 | 80 | 200 | µA | normal or pwon/listen-only mode; VTXD = VI/O (recessive) | 12 |
| VBAT input current, normal mode | IBAT | 15 | 30 | 40 | µA | normal or pwon/listen-only mode | 12 |
| VBAT input current, Standby mode | IBAT | 10 | 20 | 30 | µA | Standby mode; VCC > 4.75 V; VI/O = 2.8 V; VINH = VWAKE = VBAT = 12 V | 12 |
| VBAT input current, Sleep mode | IBAT | 10 | 20 | 30 | µA | Sleep mode; VINH = VCC = VI/O = 0 V; VWAKE = VBAT = 12 V | 12 |
| LOW-level input voltage pin TXD | VIL | -0.3 | | | V | max printed as +0.3VI/O | 12 |
| HIGH-level input current pin TXD | IIH | -5 | 0 | 5 | µA | normal or pwon/listen-only mode; VTXD = VI/O | 12 |
| LOW-level input current pin TXD | IIL | -70 | -250 | -500 | µA | normal or pwon/listen-only mode; VTXD = 0.3VI/O | 13 |
| HIGH-level output current pin RXD | IOH | -1 | -3 | -6 | mA | VRXD = VI/O − 0.4 V; VI/O = VCC | 13 |
| LOW-level output current pin RXD | IOL | 2 | 5 | 12 | mA | VRXD = 0.4 V; VTXD = VI/O; bus dominant | 13 |
| LOW-level input voltage pins STB and EN | VIL | -0.3 | | | V | max printed as +0.3VI/O | 13 |
| HIGH-level input current pins STB and EN | IIH | 1 | 4 | 10 | µA | VSTB = VEN = 0.7VI/O | 13 |
| HIGH-level output current pin ERR | IOH | -4 | -20 | -50 | µA | VERR = VI/O − 0.4 V; VI/O = VCC | 13 |
| LOW-level output current pin ERR | IOL | 0.1 | 0.2 | 0.35 | mA | VERR = 0.4 V | 13 |
| HIGH-level input current pin WAKE | IIH | -1 | -5 | -10 | µA | VWAKE = VBAT − 1.9 V | 13 |
| LOW-level input current pin WAKE | IIL | 1 | 5 | 10 | µA | VWAKE = VBAT − 3.1 V | 13 |
| dominant output voltage pin CANH | VO(dom) | 3 | 3.6 | 4.25 | V | VTXD = 0 V | 13 |
| dominant output voltage pin CANL | VO(dom) | 0.5 | 1.4 | 1.75 | V | VTXD = 0 V | 13 |
| differential bus output voltage (VCANH - VCANL), dominant | VO(dif)(bus) | 1.5 | | 3 | V | VTXD = 0 V (dominant); 45 Ω < RL < 65 Ω | 13 |
| recessive output voltage | VO(reces) | 2 | | 3 | V | normal or pwon/listen-only mode; VTXD = VI/O; no load; typ printed as 0.5VCC | 13 |
| short-circuit output current pin CANH | IO(sc) | -45 | -70 | -95 | mA | VTXD = 0 V (dominant); VCANH = 0 V | 13 |
| short-circuit output current pin CANL | IO(sc) | 45 | 70 | 95 | mA | VTXD = 0 V (dominant); VCANL = 40 V | 13 |
| differential receiver threshold voltage, normal mode | Vdif(th) | 0.5 | 0.7 | 0.9 | V | normal or pwon/listen-only mode; see Figure 7; −12 V < VCANH < 12 V; −12 V < VCANL < 12 V | 14 |
| differential receiver threshold voltage, Standby or Sleep mode | Vdif(th) | 0.4 | 0.7 | 1.15 | V | Standby or Sleep mode; −12 V < VCANH < 12 V; −12 V < VCANL < 12 V | 14 |
| differential receiver hysteresis voltage | Vhys(dif) | 50 | 70 | 100 | mV | normal or pwon/listen-only mode; see Figure 7; −12 V < VCANH < 12 V; −12 V < VCANL < 12 V | 14 |
| differential input resistance | Ri(dif) | 25 | 50 | 75 | kΩ | | 14 |
| common-mode input resistance | Ri(cm) | 15 | 25 | 35 | kΩ | | 14 |
| common-mode input capacitance | Ci(cm) | | | 20 | pF | VTXD = VCC; not tested | 14 |
| shutdown junction temperature | Tj(sd) | 155 | 165 | 180 | °C | | 15 |
| delay TXD to bus active | td(TXD-BUSon) | 25 | 70 | 110 | ns | normal mode | 14 |
| delay TXD to bus inactive | td(TXD-BUSoff) | 10 | 50 | 95 | ns | normal mode | 14 |
| delay bus active to RXD | td(BUSon-RXD) | 15 | 65 | 115 | ns | normal or pwon/listen-only mode | 14 |
| delay bus inactive to RXD | td(BUSoff-RXD) | 35 | 100 | 160 | ns | normal or pwon/listen-only mode | 14 |
| propagation delay TXD to RXD | tPD(TXD-RXD) | 40 | | 255 | ns | VSTB = 0 V | 14 |
| TXD dominant time-out | tdom(TXD) | 300 | 600 | 1000 | µs | VTXD = 0 V | 14 |
| thermal resistance from junction to ambient | Rth(j-a) | | 120 | | K/W | SO14 package; in free air | 12 |
## CAD (KiCad official)
- Symbol: `TJA1041T`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOIC-14 (KiCad packages3D, STEP)
- 3D model files: `tja1041t-etched.step` / `tja1041t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tja1041t.step` / `tja1041t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [NXP Semicon datasheet](https://www.nxp.com/docs/en/data-sheet/TJA1041.pdf) (26 pp, sha256 `7c89e2ddf157a0e3`, retrieved 2026-10-29, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tja1041t-datasheet.pdf)