component

TJA1041AT

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NXP Semicon CAN ICs, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentinterface icstja1041atfactory-2.0.0extractor-text

Verified TJA1041AT

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 14 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TJA1041AT · SOIC-14 · 14 pins
  • ✓copper: 14 copper pads, none touching another net
  • ✓datasheet: all 14 pin names found in the 25-page datasheet
  • •distributor (warn): no ['digikey'] number
  • ✓family: SOIC-14_3.9x8.7mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qaqwalxk/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • ✓package_fit: height and body within the datasheet's package drawing (datasheet p.19)
  • ✓pads: 14 pins = 14 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 14 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tja1041at.kicad_sym✓ tja1041at.kicad_mod✓ tja1041at.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 10d ago
viewers tja1041at: viewers · Ray 10d ago
package.json Publish 0.1.0 · Ray 10d ago
page.json Set visibility: public · Ray 10d ago
README.md Publish 0.1.0 · Ray 10d ago
tja1041at-etched.glb Publish 0.1.0 · Ray 10d ago
tja1041at-etched.step tja1041at: factory component page (tier=mfr) · Ray 10d ago
tja1041at-hero.glb tja1041at: hero GLB from the etched model (keeps the MPN mark) · Ray 10d ago
tja1041at-hero.overlay.json Publish 0.1.0 · Ray 10d ago
tja1041at.glb Publish 0.1.0 · Ray 10d ago
tja1041at.kicad_mod Publish 0.1.0 · Ray 10d ago
tja1041at.kicad_sym Publish 0.1.0 · Ray 10d ago
tja1041at.lbr Publish 0.1.0 · Ray 10d ago
tja1041at.step Publish 0.1.0 · Ray 10d ago
verification.json Verified: Published by the parts factory: tier mfr, 14 pins · Ray 10d ago

TJA1041AT

NXP Semicon · CAN ICs · SOIC-14

TJA1041AT from NXP Semicon, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input Transmit data input that drives the CAN bus transmitter; the datasheet gives no further limits for this pin.
2 GND power_in Ground connection for the transceiver.
3 VCC power_in Transceiver supply voltage input; the datasheet gives no voltage limits in this section.
4 RXD output Receive data output that reads out data from the bus lines.
5 VI/O power_in I/O-level adapter voltage input that sets the logic I/O levels to match the host controller supply, per the automatic I/O-level adaptation feature.
6 EN input Enable control input that, together with STB, selects the operating mode.
7 INH output Inhibit output for switching external voltage regulators; it is set floating in Sleep mode.
8 ERR output Error and power-on indication output, active LOW.
9 WAKE input Local wake-up input.
10 VBAT power_in Battery voltage input.
11 SPLIT output Common-mode stabilization output.
12 CANL bidirectional LOW-level CAN bus line.
13 CANH bidirectional HIGH-level CAN bus line.
14 STB input Standby control input, active LOW; it selects the operating mode together with EN.

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package SOIC-14
Category Interface ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
DC voltage on pin VCC VCC -0.3 6 V no time limit 11
DC voltage on pin VCC operating range VCC 4.75 5.25 V 11
DC voltage on pin VI/O VI/O -0.3 6 V no time limit 11
DC voltage on pin VI/O operating range VI/O 2.8 5.25 V 11
DC voltage on pin VBAT VBAT -0.3 40 V no time limit 11
DC voltage on pin VBAT operating range VBAT 5 27 V 11
DC voltage on pin VBAT load dump VBAT 40 V load dump 11
DC voltage on pin TXD VTXD -0.3 V 11
DC voltage on pin RXD VRXD -0.3 V 11
DC voltage on pin STB VSTB -0.3 V 11
DC voltage on pin EN VEN -0.3 V 11
DC voltage on pin ERR VERR -0.3 V 11
DC voltage on pin INH VINH -0.3 V 11
DC voltage on pin WAKE VWAKE -0.3 V 11
DC current on pin WAKE IWAKE -15 mA 11
DC voltage on pin CANH VCANH -27 40 V 0 < VCC < 5.25 V; no time limit 11
DC voltage on pin CANL VCANL -27 40 V 0 < VCC < 5.25 V; no time limit 11
DC voltage on pin SPLIT VSPLIT -27 40 V 0 < VCC < 5.25 V; no time limit 11
Transient voltages on pins CANH, CANL, SPLIT and VBAT Vtrt -200 200 V according to ISO 7637; see Figure 6 11
Electrostatic discharge voltage HBM, pins CANH, CANL and SPLIT Vesd -6 6 kV Human Body Model (HBM) 11
Electrostatic discharge voltage HBM, pins TXD, RXD, VI/O and STB Vesd -3 3 kV Human Body Model (HBM) 11
Electrostatic discharge voltage HBM, all other pins Vesd -4 4 kV Human Body Model (HBM) 11
Electrostatic discharge voltage Machine Model (MM) Vesd -200 200 V Machine Model (MM) 11
Virtual junction temperature Tvj -40 150 °C 11
Storage temperature Tstg -55 150 °C 11
VCC undervoltage detection level for forced Sleep mode VCC(sleep) 2.75 3.3 4.5 V VBAT = 12 V (fail-safe) 12
VI/O undervoltage detection level for forced Sleep mode VI/O(sleep) 0.5 1.5 2 V 12
VBAT voltage level for fail-safe fallback mode VBAT(stb) 2.75 3.3 4.5 V VCC = 5 V (fail-safe) 12
VBAT voltage level for setting pwon flag VBAT(pwon) 2.5 3.3 4.1 V VCC = 0 V 12
VCC input current, normal mode, dominant ICC 25 55 80 mA normal mode; VTXD = 0 V (dominant) 12
VCC input current, normal or pwon/listen-only mode, recessive ICC 2 6 10 mA normal or pwon/listen-only mode; VTXD = VI/O (recessive) 12
VCC input current, standby or sleep mode ICC 1 10 µA standby or sleep mode 12
VI/O input current, normal mode, dominant II/O 100 350 1000 µA normal mode; VTXD = 0 V (dominant) 12
VI/O input current, normal or pwon/listen-only mode, recessive II/O 15 80 200 µA normal or pwon/listen-only mode; VTXD = VI/O (recessive) 12
VBAT input current, normal or pwon/listen-only mode IBAT 15 30 40 µA normal or pwon/listen-only mode 12
VBAT input current, standby mode IBAT 10 20 30 µA standby mode; VCC > 4.75 V; VI/O = 2.8 V; VINH = VWAKE = VBAT = 12 V 12
VBAT input current, sleep mode IBAT 10 20 30 µA sleep mode; VINH = VCC = VI/O = 0 V; VWAKE = VBAT = 12 V 12
LOW-level input voltage (pin TXD) VIL -0.3 V 12
HIGH-level input current (pin TXD) IIH -5 0 5 µA normal or pwon/listen-only mode; VTXD = VI/O 12
LOW-level input current (pin TXD) IIL -70 -250 -500 µA normal or pwon/listen-only mode; VTXD = 0.3VI/O 12
HIGH-level output current (pin RXD) IOH -1 -3 -6 mA VRXD = VI/O − 0.4 V; VI/O = VCC 13
LOW-level output current (pin RXD) IOL 2 5 12 mA VRXD = 0.4 V; VTXD = VI/O; bus dominant 13
HIGH-level input current (pins STB and EN) IIH 1 4 10 µA VSTB = VEN = 0.7VI/O 13
LOW-level input current (pins STB and EN) IIL 0 -1 µA VSTB = VEN = 0 V 13
HIGH-level output current (pin ERR) IOH -4 -20 -50 µA VERR = VI/O − 0.4 V; VI/O = VCC 13
LOW-level output current (pin ERR) IOL 0.1 0.2 0.35 mA VERR = 0.4 V 13
Dominant output voltage, pin CANH VO(dom) 3 3.6 4.25 V VTXD = 0 V; pin CANH 13
Dominant output voltage, pin CANL VO(dom) 0.5 1.4 1.75 V VTXD = 0 V; pin CANL 13
Differential bus output voltage, dominant VO(dif)(bus) 1.5 3 V VTXD = 0 V (dominant); 45 Ω < RL < 65 Ω 13
Differential bus output voltage, recessive VO(dif)(bus) -50 50 mV VTXD = VI/O (recessive); no load 13
Recessive output voltage, normal or pwon/listen-only mode VO(reces) 2 3 V normal or pwon/listen-only mode; VTXD = VI/O; no load 13
Short-circuit output current, pin CANH IO(sc) -40 -70 -95 mA VTXD = 0 V (dominant); pin CANH; VCANH = 0 V 13
Short-circuit output current, pin CANL IO(sc) 40 70 95 mA VTXD = 0 V (dominant); pin CANL; VCANL = 40 V 13
Differential receiver threshold voltage, normal mode Vdif(th) 0.5 0.7 0.9 V normal or pwon/listen-only mode (see Figure 7); −12 V < VCANH < 12 V; −12 V < VCANL < 12 V 14
Delay TXD to bus active td(TXD-BUSon) 25 70 110 ns normal mode 14
Delay bus active to RXD td(BUSon-RXD) 15 65 115 ns normal or pwon/listen-only mode 14
Delay bus inactive to RXD td(BUSoff-RXD) 35 100 160 ns normal or pwon/listen-only mode 14
Propagation delay TXD to RXD tPD(TXD-RXD) 40 255 ns VSTB = 0 V 14
TXD dominant time-out tdom(TXD) 300 600 1000 µs VTXD = 0 V 14
Shutdown junction temperature (thermal resistance context: junction to ambient in SO14) Rth(j-a) 120 K/W in free air 12

CAD (KiCad official)

  • Symbol: TJA1041AT
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: tja1041at-etched.step / tja1041at-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tja1041at.step / tja1041at.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (25 pp, sha256 a05cab8d4394678b, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF