component
TISP61089QBDR-S
Public Made by Adomby adom
BOURNS ESD Protection Devices, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TISP61089QBDR-S
BOURNS · ESD Protection Devices · SOIC-8
TISP61089QBDR-S from BOURNS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K1 | passive | Cathode of thyristor/diode element 1, connected to a protected SLIC line terminal (tip/ring side). |
| 2 | G1,G2 | input | Common gate for elements 1 and 2, connected to the SLIC negative supply (VGG) via the 100 nF decoupling capacitor to set the protection voltage (-20 V to -155 V programming range). |
| 3 | G3,G4 | input | Common gate for elements 3 and 4, connected to the SLIC negative supply (VGG) via the 100 nF decoupling capacitor to set the protection voltage (-20 V to -155 V programming range). |
| 4 | K3 | passive | Cathode of thyristor/diode element 3, connected to a protected SLIC line terminal. |
| 5 | K4 | passive | Cathode of thyristor/diode element 4, connected to a protected SLIC line terminal. |
| 6 | A | passive | Common anode of all four elements, connected to ground (0 V); internally joined to pin 7. |
| 7 | A | passive | Common anode of all four elements, connected to ground (0 V); internally joined to pin 6. |
| 8 | K2 | passive | Cathode of thyristor/diode element 2, connected to a protected SLIC line terminal. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | BOURNS |
| Package | SOIC-8 |
| Category | Circuit Protection |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Repetitive peak off-state voltage | VDRM | -170 | V | IG = 0, -40 °C ≤ TJ ≤ 85 °C | 2 | ||
| Repetitive peak gate-cathode voltage | VGKRM | -167 | V | VKA = 0, -40 °C ≤ TJ ≤ 85 °C | 2 | ||
| Non-repetitive peak on-state pulse current 10/1000 µs | ITSP | 30 | A | 10/1000 µs (Bellcore GR-1089-CORE) | 2 | ||
| Non-repetitive peak on-state pulse current 5/320 µs | ITSP | 40 | A | 5/320 (ITU-T K.20/21/45, YD/T-950, open circuit voltage waveshape 10/700) | 2 | ||
| Non-repetitive peak on-state pulse current 2/10 µs | ITSP | 120 | A | 2/10 (Bellcore GR-1089-CORE) | 2 | ||
| Non-repetitive peak on-state current, 60 Hz | ITSM | 0.5 | A | 60 Hz, 900 s | 2 | ||
| Non-repetitive peak gate current | IGSM | 40 | A | 2/10 µs pulse, cathodes commoned | 2 | ||
| Junction temperature | TJ | -40 | 150 | °C | 2 | ||
| Storage temperature range | Tstg | -40 | 150 | °C | 2 | ||
| Gate decoupling capacitor | CG | 100 | nF | 2 | |||
| Series resistor for first-level and second-level surge survival | RS | 40 | Ω | 2 | |||
| Series resistor for first-level surge survival | RS | 25 | Ω | 2 | |||
| Off-state current | ID | -5 | µA | VD = VDRM, VGK = 0 | 2 | ||
| Breakover voltage | V(BO) | -64 | V | 10/700 µs, IT = -40 A, RS = 55 Ω, VGG = -48 V, CG = 100nF | 2 | ||
| Forward voltage | VF | 3 | V | IF = 5 A, tw = 200 µs | 2 | ||
| Peak forward recovery voltage | VFRM | 12 | V | 10/700 µs, IF = 40 A, RS = 55 Ω, VGG = -48 V, CG = 100nF | 2 | ||
| Holding current | IH | -150 | mA | IT = -1 A, di/dt = 1 A/ms, VGG = -100 V | 2 | ||
| Gate reverse current | IGAS | -5 | µA | VGG = VGK = VGKRM, VKA = 0 | 2 | ||
| Gate trigger current | IGT | 5 | mA | IT = 3 A, tp(g) ≥ 20 µs, VGG = -100 V | 2 | ||
| Gate trigger voltage | VGT | 2.5 | V | IT = 3 A, tp(g) ≥ 20 µs, VGG = -100 V | 2 | ||
| Anode-cathode off-state capacitance | CAK | 100 | pF | f = 1 MHz, Vd = 1 V, IG = 0, VD = -3V | 2 | ||
| Anode-cathode off-state capacitance | CAK | 50 | pF | f = 1 MHz, Vd = 1 V, IG = 0, VD = -48V | 2 | ||
| Junction to free air thermal resistance | RθJA | 160 | °C/W | Ptot = 0.8 W, TA = 25 °C, 5 cm2, FR4 PCB | 3 |
CAD (KiCad official)
- Symbol:
TISP61089QBDR-S - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tisp61089qbdr-s-etched.step/tisp61089qbdr-s-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tisp61089qbdr-s.step/tisp61089qbdr-s.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: BOURNS datasheet (5 pp, sha256
342e7f5717b241f3, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TISP61089QBDR-S
**BOURNS** · ESD Protection Devices · SOIC-8
TISP61089QBDR-S from BOURNS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K1 | passive | Cathode of thyristor/diode element 1, connected to a protected SLIC line terminal (tip/ring side). |
| 2 | G1,G2 | input | Common gate for elements 1 and 2, connected to the SLIC negative supply (VGG) via the 100 nF decoupling capacitor to set the protection voltage (-20 V to -155 V programming range). |
| 3 | G3,G4 | input | Common gate for elements 3 and 4, connected to the SLIC negative supply (VGG) via the 100 nF decoupling capacitor to set the protection voltage (-20 V to -155 V programming range). |
| 4 | K3 | passive | Cathode of thyristor/diode element 3, connected to a protected SLIC line terminal. |
| 5 | K4 | passive | Cathode of thyristor/diode element 4, connected to a protected SLIC line terminal. |
| 6 | A | passive | Common anode of all four elements, connected to ground (0 V); internally joined to pin 7. |
| 7 | A | passive | Common anode of all four elements, connected to ground (0 V); internally joined to pin 6. |
| 8 | K2 | passive | Cathode of thyristor/diode element 2, connected to a protected SLIC line terminal. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | BOURNS |
| Package | SOIC-8 |
| Category | Circuit Protection |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Repetitive peak off-state voltage | VDRM | -170 | | | V | IG = 0, -40 °C ≤ TJ ≤ 85 °C | 2 |
| Repetitive peak gate-cathode voltage | VGKRM | -167 | | | V | VKA = 0, -40 °C ≤ TJ ≤ 85 °C | 2 |
| Non-repetitive peak on-state pulse current 10/1000 µs | ITSP | | | 30 | A | 10/1000 µs (Bellcore GR-1089-CORE) | 2 |
| Non-repetitive peak on-state pulse current 5/320 µs | ITSP | | | 40 | A | 5/320 (ITU-T K.20/21/45, YD/T-950, open circuit voltage waveshape 10/700) | 2 |
| Non-repetitive peak on-state pulse current 2/10 µs | ITSP | | | 120 | A | 2/10 (Bellcore GR-1089-CORE) | 2 |
| Non-repetitive peak on-state current, 60 Hz | ITSM | | | 0.5 | A | 60 Hz, 900 s | 2 |
| Non-repetitive peak gate current | IGSM | | | 40 | A | 2/10 µs pulse, cathodes commoned | 2 |
| Junction temperature | TJ | -40 | | 150 | °C | | 2 |
| Storage temperature range | Tstg | -40 | | 150 | °C | | 2 |
| Gate decoupling capacitor | CG | | 100 | | nF | | 2 |
| Series resistor for first-level and second-level surge survival | RS | 40 | | | Ω | | 2 |
| Series resistor for first-level surge survival | RS | 25 | | | Ω | | 2 |
| Off-state current | ID | | | -5 | µA | VD = VDRM, VGK = 0 | 2 |
| Breakover voltage | V(BO) | | | -64 | V | 10/700 µs, IT = -40 A, RS = 55 Ω, VGG = -48 V, CG = 100nF | 2 |
| Forward voltage | VF | | | 3 | V | IF = 5 A, tw = 200 µs | 2 |
| Peak forward recovery voltage | VFRM | | | 12 | V | 10/700 µs, IF = 40 A, RS = 55 Ω, VGG = -48 V, CG = 100nF | 2 |
| Holding current | IH | -150 | | | mA | IT = -1 A, di/dt = 1 A/ms, VGG = -100 V | 2 |
| Gate reverse current | IGAS | | | -5 | µA | VGG = VGK = VGKRM, VKA = 0 | 2 |
| Gate trigger current | IGT | | | 5 | mA | IT = 3 A, tp(g) ≥ 20 µs, VGG = -100 V | 2 |
| Gate trigger voltage | VGT | | | 2.5 | V | IT = 3 A, tp(g) ≥ 20 µs, VGG = -100 V | 2 |
| Anode-cathode off-state capacitance | CAK | | | 100 | pF | f = 1 MHz, Vd = 1 V, IG = 0, VD = -3V | 2 |
| Anode-cathode off-state capacitance | CAK | | | 50 | pF | f = 1 MHz, Vd = 1 V, IG = 0, VD = -48V | 2 |
| Junction to free air thermal resistance | RθJA | | | 160 | °C/W | Ptot = 0.8 W, TA = 25 °C, 5 cm2, FR4 PCB | 3 |
## CAD (KiCad official)
- Symbol: `TISP61089QBDR-S`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tisp61089qbdr-s-etched.step` / `tisp61089qbdr-s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tisp61089qbdr-s.step` / `tisp61089qbdr-s.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [BOURNS datasheet](docs/tisp61089qbdr-s-datasheet.pdf) (5 pp, sha256 `342e7f5717b241f3`, retrieved 2026-10-23, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tisp61089qbdr-s-datasheet.pdf)