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THVD1505DR

Public Made by Adom

by adom

Texas Instruments RS-485 / RS-422 ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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THVD1505DR

Texas Instruments · RS-485 / RS-422 ICs · SOIC-8

THVD1505DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 R output Receive data output (digital output) from the receiver.
2 RE input Receiver enable, active low, with an internal 5-MΩ pull-up.
3 DE input Driver enable, active high, with an internal 5-MΩ pull-down.
4 D input Driver data input with an internal 5-MΩ pull-up.
5 GND power_in Device ground.
6 A bidirectional Bus pin acting as driver output or receiver input, complementary to B; absolute bus voltage limit is −18 V to 18 V with respect to GND.
7 B bidirectional Bus pin acting as driver output or receiver input, complementary to A; absolute bus voltage limit is −18 V to 18 V with respect to GND.
8 VCC power_in Supply pin, 4.5 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Interface
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V over operating free-air temperature range 3
Input voltage at any logic pin (D, DE or RE) VL -0.3 5.7 V over operating free-air temperature range 3
Voltage at A or B inputs VA, VB -18 18 V as differential or common-mode with respect to GND 3
Receiver output current IO -24 24 mA over operating free-air temperature range 3
Junction temperature TJ 170 °C 3
Storage temperature TSTG -65 150 °C 3
ESD HBM, bus terminals and GND V(ESD) -16000 16000 V Human body model per ANSI/ESDA/JEDEC JS-001 3
ESD HBM, all other pins V(ESD) -4000 4000 V Human body model per ANSI/ESDA/JEDEC JS-001 3
ESD CDM V(ESD) -1500 1500 V Charged-device model per JEDEC JESD22-C101 3
ESD IEC 61000-4-2 contact discharge, bus terminals and GND V(ESD) -8000 8000 V IEC 61000-4-2 4
ESD IEC 61000-4-2 air-gap discharge, bus terminals and GND V(ESD) -8000 8000 V IEC 61000-4-2 4
ESD IEC 61000-4-4 EFT fast transient, bus terminals and GND V(ESD) -2000 2000 V IEC 61000-4-4 4
Supply voltage VCC 4.5 5 5.5 V 4
Differential input voltage VID -12 12 V 4
Input voltage at any bus terminal VI -7 12 V 4
High-level input voltage (driver, driver-enable, receiver-enable inputs) VIH 2 V printed maximum is VCC; not numeric 4
Low-level input voltage (driver, driver-enable, receiver-enable inputs) VIL 0 0.8 V 4
Driver output current IO -60 60 mA Driver 4
Receiver output current IO -8 8 mA Receiver 4
Differential load resistance RL 54 60 Ω 4
Signaling rate 1/tUI 0.3 1000 kbps 4
Junction temperature TJ -40 150 °C 4
Operating ambient temperature TA -40 125 °C 4
Driver differential-output voltage magnitude /VOD/ 1.5 2.5 V Vtest from -7 to +12 V, see Figure 7 5
Driver differential-output voltage magnitude /VOD/ 2 3 V RL = 100 Ω (RS-422), CL = 50 pF 5
Change in magnitude of driver differential-output voltage Δ/VOD/ -50 50 mV RL = 54 Ω, CL = 50 pF, see Figure 8 5
Steady-state common-mode output voltage VOC(SS) 1 3 V RL = 54 Ω, CL = 50 pF, see Figure 8 5
Change in differential driver common-mode output voltage ΔVOC -50 50 mV 5
Peak-to-peak driver common-mode output voltage VOC(PP) 250 mV 5
Driver short-circuit output current /IOS/ 150 mA DE = VCC, -7 V ≤ [VA or VB] ≤ 12 V, or A pin shorted to B pin 5
Bus input current (driver disabled) II 75 110 µA DE = 0 V, VCC = 0 V or 5.5 V, VI = 12 V 5
Bus input current (driver disabled) II -90 -70 µA DE = 0 V, VCC = 0 V or 5.5 V, VI = -7 V 5
Bus input impedance RA, RB 96 kΩ VA = -7 V, VB = 12 V and VA = 12 V, VB = -7 V, see Figure 12 5
Positive-going receiver differential-input voltage threshold VIT+ 60 100 mV 5
Negative-going receiver differential-input voltage threshold VIT- -100 -60 mV 5
Receiver differential-input voltage threshold hysteresis (VIT+, VIT-) VHYS 40 120 mV 5
Receiver high-level output voltage VOH 4 V IOH = -8 mA 5
Receiver low-level output voltage VOL 0.2 0.4 V IOL = 8 mA 5
Receiver high-impedance output current IOZ -1 1 µA VO = 0 V or VCC, RE = VCC 5
Receiver output short-circuit current IOSR 95 mA RE = 0, DE = 0, see Figure 13 5
Input current (D, DE, RE) IIN -2 2 µA 5
Supply current (quiescent), driver and receiver enabled ICC 820 1100 µA DE = VCC, RE = 0, no load 5
Supply current (quiescent), driver enabled, receiver disabled ICC 520 660 µA DE = VCC, RE = VCC, no load 5
Supply current (quiescent), driver disabled, receiver enabled ICC 520 660 µA DE = 0, RE = 0, no load 5
Supply current (quiescent), driver and receiver disabled ICC 0.03 1 µA DE = 0, RE = VCC, no load 5
Driver differential output rise and fall times tr, tf 100 115 300 ns See Figure 9 6
Driver propagation delay tPHL, tPLH 90 350 ns See Figure 9 6
Driver pulse skew tSK(P) 25 40 ns See Figure 9 6
Driver disable time tPHZ, tPLZ 70 160 ns See Figure 10 and Figure 11 6
Driver enable time, receiver enabled tPHZ, tPLZ 220 400 ns Receiver enabled, see Figure 10 and Figure 11 6
Driver enable time, receiver disabled tPHZ, tPLZ 1.5 3 µs Receiver disabled, see Figure 10 and Figure 11 6
Receiver output rise and fall times tr, tf 6 30 ns See Figure 14 6
Receiver propagation delay time tPHL, tPLH 80 120 ns See Figure 14 6
Receiver pulse skew tSK(P) 2 7 ns See Figure 14 6
Receiver disable time tPHZ, tPLZ 15 30 ns See Figure 15 6
Receiver enable time, driver enabled tPZL, tPZH 180 370 ns Driver enabled, see Figure 15 6
Receiver enable time, driver disabled tPZL, tPZH 1 5 µs Driver disabled, see Figure 16 6
Bus fail-safe time tFS 25 35 45 ms Driver disabled, see Figure 17 6
Junction-to-ambient thermal resistance RθJA 125.3 °C/W D (SOIC) 8-pin package 4

CAD (KiCad official)

  • Symbol: THVD1505DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: thvd1505dr-etched.step / thvd1505dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); thvd1505dr.step / thvd1505dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 c2b91e56d83f8f64, retrieved 2026-10-18, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF