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THVD1428DR
Public Made by Adomby adom
Texas Instruments RS-485/RS-422 ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTHVD1428DR
Texas Instruments · RS-485/RS-422 ICs · SOIC-8
THVD1428DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | R | output | Receive data output. |
| 2 | RE | input | Receiver enable, active low, with 2-MΩ internal pull-up. |
| 3 | DE | input | Driver enable, active high, with 2-MΩ internal pull-down. |
| 4 | D | input | Driver data input with 2-MΩ internal pull-up. |
| 5 | GND | power_in | Device ground. |
| 6 | A | bidirectional | Bus I/O port A (complementary to B), with ±16 kV HBM ESD and ±3 kV IEC surge protection. |
| 7 | B | bidirectional | Bus I/O port B (complementary to A), with ±16 kV HBM ESD and ±3 kV IEC surge protection. |
| 8 | VCC | power_in | 3.3-V to 5-V supply (3 V to 5.5 V operating range). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | -0.5 | 7 | V | 4 | ||
| Bus voltage | -15 | 15 | V | Range at any bus pin (A or B) as differential or common-mode with respect to GND | 4 | ||
| Input voltage | -0.3 | 5.7 | V | Range at any logic pin (D, DE, or /RE) | 4 | ||
| Receiver output current | IO | -24 | 24 | mA | 4 | ||
| Storage temperature range | Tstg | -65 | 150 | ℃ | 4 | ||
| HBM ESD, bus terminals and GND | V(ESD) | -16 | 16 | kV | Human body model, per ANSI/ESDA/JEDEC JS-001, bus terminals and GND | 4 | |
| Surge | V(surge) | -3 | 3 | kV | Per IEC 61000-4-5, 1.2/50 μs, bus pins and GND | 4 | |
| Supply voltage | VCC | 3 | 5.5 | V | 5 | ||
| Input voltage at any bus terminal | VI | -12 | 12 | V | Separately or common mode | 5 | |
| High-level input voltage | VIH | 2 | V | Driver, driver enable, and receiver enable inputs; max is VCC | 5 | ||
| Low-level input voltage | VIL | 0 | 0.8 | V | Driver, driver enable, and receiver enable inputs | 5 | |
| Differential input voltage | VID | -12 | 12 | V | 5 | ||
| Output current, driver | IO | -60 | 60 | mA | 5 | ||
| Output current, receiver | IOR | -8 | 8 | mA | 5 | ||
| Differential load resistance | RL | 54 | Ω | 5 | |||
| Signaling rate | 1/tUI | 20 | Mbps | THVD1428 | 5 | ||
| Operating ambient temperature | TA | -40 | 125 | ℃ | 5 | ||
| Junction temperature | TJ | -40 | 150 | ℃ | 5 | ||
| Driver differential output voltage magnitude | /VOD/ | 1.5 | 3.5 | V | RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, see Figure 7 | 6 | |
| Driver differential output voltage magnitude | /VOD/ | 2.1 | V | RL = 60 Ω, -12 V ≤ Vtest ≤ 12 V, 4.5 V ≤ VCC ≤ 5.5 V, see Figure 7 | 6 | ||
| Driver differential output voltage magnitude | /VOD/ | 2 | 4 | V | RL = 100 Ω, see Figure 8 | 6 | |
| Change in differential output voltage | Δ/VOD/ | -200 | 200 | mV | RL = 54 Ω, see Figure 8 | 6 | |
| Common-mode output voltage | VOC | 1 | 3 | V | typ printed as VCC / 2 | 6 | |
| Change in steady-state common-mode output voltage | ΔVOC(SS) | -200 | 200 | mV | 6 | ||
| Short-circuit output current | IOS | -250 | 250 | mA | DE = VCC, -7 V ≤ VO ≤ 12 V | 6 | |
| Bus input current | II | 50 | 125 | µA | DE = 0 V, VCC = 0 V or 5.5 V, VI = 12 V | 6 | |
| Bus input current | II | -100 | -65 | µA | DE = 0 V, VCC = 0 V or 5.5 V, VI = -7 V | 6 | |
| Bus input current | II | -150 | -100 | µA | DE = 0 V, VCC = 0 V or 5.5 V, VI = -12 V | 6 | |
| Positive-going input threshold voltage | VTH+ | -100 | -20 | mV | Over common-mode range of ±12 V | 6 | |
| Negative-going input threshold voltage | VTH- | -200 | -130 | mV | Over common-mode range of ±12 V | 6 | |
| Input hysteresis | VHYS | 30 | mV | 6 | |||
| Input differential capacitance | CA,B | 220 | pF | Measured between A and B, f = 1 MHz | 6 | ||
| Output low voltage | VOL | 0.2 | 0.4 | V | IOL = 8 mA | 6 | |
| Output high-impedance current | IOZR | -1 | 1 | µA | VO = 0 V or VCC, RE = VCC | 6 | |
| Input current (D, DE, RE) | IIN | -6.2 | 6.2 | µA | 4.5 V ≤ VCC ≤ 5.5 V | 6 | |
| Supply current, driver and receiver enabled | ICC | 2.4 | 3 | mA | RE = 0 V, DE = VCC, No load | 6 | |
| Supply current, driver enabled, receiver disabled | ICC | 2 | 2.6 | mA | RE = VCC, DE = VCC, No load | 6 | |
| Supply current, driver disabled, receiver enabled | ICC | 700 | 960 | µA | RE = 0 V, DE = 0V, No load | 6 | |
| Supply current, driver and receiver disabled | ICC | 0.1 | 2 | µA | RE = VCC, DE = 0 V, D = open, No load | 6 | |
| Thermal shutdown temperature | TSD | 170 | ℃ | 6 | |||
| Driver differential output rise / fall time | tr, tf | 9 | 16 | ns | RL = 54 Ω, CL = 50 pF, see Figure 9 | 7 | |
| Driver propagation delay | tPHL, tPLH | 12 | 25 | ns | RL = 54 Ω, CL = 50 pF, see Figure 9 | 7 | |
| Driver pulse skew | tSK(P) | 6 | ns | /tPHL, tPLH/, RL = 54 Ω, CL = 50 pF, see Figure 9 | 7 | ||
| Driver disable time | tPHZ, tPLZ | 18 | 40 | ns | see Figure 10 and Figure 11 | 7 | |
| Driver enable time | tPZH, tPZL | 16 | 40 | ns | RE = 0 V, see Figure 10 and Figure 11 | 7 | |
| Driver enable time | tPZH, tPZL | 2.8 | 11 | µs | RE = VCC, see Figure 10 and Figure 11 | 7 | |
| Receiver output rise / fall time | tr, tf | 2 | 6 | ns | CL = 15 pF, see Figure 12 | 7 | |
| Receiver propagation delay | tPHL, tPLH | 12 | 45 | ns | CL = 15 pF, see Figure 12 | 7 | |
| Receiver pulse skew | tSK(P) | 6 | ns | /tPHL, tPLH/, CL = 15 pF, see Figure 12 | 7 | ||
| Receiver disable time | tPHZ, tPLZ | 14 | 28 | ns | CL = 15 pF, see Figure 12 | 7 | |
| Receiver enable time | tPZH, tPZL | 75 | 110 | ns | DE = VCC, see Figure 13 | 7 | |
| Receiver enable time | tPZH, tPZL | 4.8 | 14 | µs | DE = 0 V, see Figure 14 | 7 | |
| Junction-to-ambient thermal resistance | RθJA | 120.7 | °C/W | D (SOIC) 8-pin | 5 | ||
| Junction-to-case (top) thermal resistance | RθJC(top) | 50.3 | °C/W | D (SOIC) 8-pin | 5 | ||
| Junction-to-board thermal resistance | RθJB | 62.8 | °C/W | D (SOIC) 8-pin | 5 |
CAD (KiCad official)
- Symbol:
THVD1428DR - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
thvd1428dr-etched.step/thvd1428dr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);thvd1428dr.step/thvd1428dr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
897ee4c0c18cb9ce, retrieved 2026-10-23, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).