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THS7373IPWR
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Texas Instruments Operational Amplifier, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTHS7373IPWR
Texas Instruments · Operational Amplifier · TSSOP-14
THS7373IPWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CVBS IN | input | CVBS filter video input. |
| 2 | HD CH.1 IN | input | HD channel 1 video input. |
| 3 | HD CH.2 IN | input | HD channel 2 video input. |
| 4 | HD CH.3 IN | input | HD channel 3 video input. |
| 5 | GND | power_in | Ground pin for all internal circuitry. |
| 6 | DISABLE | input | Logic high disables the part and logic low enables it; must not be left floating and must be tied to a defined logic state (GND or VS+). |
| 7 | NC | unconnected | No internal connection. |
| 8 | NC | unconnected | No internal connection. |
| 9 | HD BYPASS | input | Logic high bypasses the internal HD low-pass filter and logic low uses the internal filters; must not be left floating and must be tied to a defined logic state (GND or VS+). |
| 10 | VS+ | power_in | Positive power-supply pin; connect to +3 V to +5 V. |
| 11 | HD CH3 OUT | output | HD channel 3 video output. |
| 12 | HD CH2 OUT | output | HD channel 2 video output. |
| 13 | HD CH1 OUT | output | HD channel 1 video output. |
| 14 | CVBS OUT | output | CVBS filter video output. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Amplifiers |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VS+ | 3 | 5.5 | V | 2 | ||
| Ambient temperature | TA | -40 | 25 | 85 | °C | 2 | |
| Supply voltage VS+ to GND | VS+ | 5.5 | V | 2 | |||
| Input voltage | VI | -0.4 | V | to VS+ upper | 2 | ||
| Output current | IO | -90 | 90 | mA | 2 | ||
| Maximum junction temperature, any condition | TJ | 150 | °C | 2 | |||
| Maximum junction temperature, continuous operation | TJ | 125 | °C | long-term reliability | 2 | ||
| Storage temperature | TSTG | -60 | 150 | °C | 2 | ||
| ESD HBM | 2500 | V | Human body model | 2 | |||
| ESD CDM | 1000 | V | Charge device model | 2 | |||
| ESD MM | 200 | V | Machine model | 2 | |||
| Thermal resistance junction-to-case | θJC | 38 | °C/W | TSSOP-14 (PW) | 2 | ||
| Thermal resistance junction-to-ambient | θJA | 115 | °C/W | JEDEC High-K PCB; 130 for low-K | 2 | ||
| CVBS passband bandwidth | 7 | 8.2 | 10.2 | MHz | VS+=3.3 V; -1 dB; VO = 0.2 VPP and 2 VPP | 3 | |
| CVBS bandwidth | 7.8 | 9.5 | 11.4 | MHz | VS+=3.3 V; -3 dB; VO = 0.2 VPP and 2 VPP | 3 | |
| CVBS attenuation at 6.75 MHz | -0.9 | 0.2 | 1.1 | dB | VS+=3.3 V; with respect to 500 kHz, f = 6.75 MHz | 3 | |
| CVBS attenuation at 27 MHz | 42 | 54 | dB | VS+=3.3 V; with respect to 500 kHz, f = 27 MHz | 3 | ||
| CVBS gain | 5.7 | 6 | 6.3 | dB | VS+=3.3 V; TA = +25°C | 3 | |
| CVBS gain over temperature | 5.65 | 6.35 | dB | VS+=3.3 V; TA = -40°C to +85°C | 3 | ||
| HD passband bandwidth | 27.8 | 33 | 38.8 | MHz | VS+=3.3 V; -1 dB; VO = 0.2 VPP and 2 VPP | 3 | |
| HD bandwidth | 30.3 | 36 | 42.5 | MHz | VS+=3.3 V; -3 dB; VO = 0.2 VPP and 2 VPP | 3 | |
| HD bypass mode bandwidth | 170 | 350 | MHz | VS+=3.3 V; -3 dB; VO = 0.2 VPP | 3 | ||
| HD slew rate | 400 | 450 | V/μs | VS+=3.3 V; Bypass mode; VO = 2 VPP | 3 | ||
| HD attenuation at 27 MHz | -1 | -0.1 | 1 | dB | VS+=3.3 V; with respect to 500 kHz, f = 27 MHz | 3 | |
| HD attenuation at 74 MHz | 34 | 40 | dB | VS+=3.3 V; with respect to 500 kHz, f = 74 MHz | 3 | ||
| HD gain | 5.7 | 6 | 6.3 | dB | VS+=3.3 V; All channels, TA = +25°C | 3 | |
| HD gain over temperature | 5.65 | 6.35 | dB | VS+=3.3 V; All channels, TA = -40°C to +85°C | 3 | ||
| Biased output voltage CVBS | 200 | 300 | 400 | mV | VS+=3.3 V; VIN = 0 V, CVBS channel | 4 | |
| Biased output voltage HD | 200 | 300 | 400 | mV | VS+=3.3 V; VIN = 0 V, HD channels | 4 | |
| Sync-tip clamp charge current CVBS | 140 | 200 | μA | VS+=3.3 V; VIN = -0.1 V, CVBS channel | 4 | ||
| Sync-tip clamp charge current HD | 280 | 400 | μA | VS+=3.3 V; VIN = -0.1 V, HD channels | 4 | ||
| High output voltage swing | 2.85 | 3.1 | V | VS+=3.3 V; RL = 150 Ω to GND | 4 | ||
| Low output voltage swing | 0.03 | 0.1 | V | VS+=3.3 V; RL = 150 Ω to GND (VIN = -0.2 V) | 4 | ||
| Operating voltage (3.3 V table) | 2.6 | 3.3 | 5.5 | V | 4 | ||
| Total quiescent current, enabled | IQ | 13.4 | 16.2 | 21 | mA | VS+=3.3 V; VIN = 0 V, all channels on, no load | 4 |
| Total quiescent current, disabled | IQ | 0.1 | 10 | μA | VS+=3.3 V; VIN = 0 V, all channels off, VDISABLE = 3 V | 4 | |
| Logic high threshold | VIH | 1.8 | 2 | V | VS+=3.3 V; Disabled or Bypass mode | 4 | |
| Logic low threshold | VIL | 0.65 | 0.7 | V | VS+=3.3 V; Enabled or Filter mode | 4 | |
| CVBS passband bandwidth (5 V) | 7 | 8.2 | 10.2 | MHz | VS+=5 V; -1 dB; VO = 0.2 VPP and 2 VPP | 5 | |
| CVBS bandwidth (5 V) | 7.8 | 9.5 | 11.4 | MHz | VS+=5 V; -3 dB; VO = 0.2 VPP and 2 VPP | 5 | |
| CVBS attenuation at 6.75 MHz (5 V) | -0.9 | 0.2 | 1.1 | dB | VS+=5 V; with respect to 500 kHz, f = 6.75 MHz | 5 | |
| CVBS attenuation at 27 MHz (5 V) | 42 | 54 | dB | VS+=5 V; with respect to 500 kHz, f = 27 MHz | 5 | ||
| CVBS gain (5 V) | 5.7 | 6 | 6.3 | dB | VS+=5 V; TA = +25°C | 5 | |
| HD bandwidth (5 V) | 30.3 | 36 | 42.5 | MHz | VS+=5 V; -3 dB; VO = 0.2 VPP and 2 VPP | 5 | |
| HD gain (5 V) | 5.7 | 6 | 6.3 | dB | VS+=5 V; All channels, TA = +25°C | 5 | |
| High output voltage swing (5 V) | 4.5 | 4.75 | V | VS+=5 V; RL = 150 Ω to GND | 6 | ||
| Low output voltage swing (5 V) | 0.03 | 0.1 | V | VS+=5 V; RL = 150 Ω to GND (VIN = -0.2 V) | 6 | ||
| Operating voltage (5 V table) | 2.6 | 5 | 5.5 | V | 6 | ||
| Total quiescent current, enabled (5 V) | IQ | 14 | 16.9 | 22 | mA | VS+=5 V; VIN = 0 V, all channels on, no load | 6 |
| Total quiescent current, disabled (5 V) | IQ | 1 | 10 | μA | VS+=5 V; VIN = 0 V, all channels off, VDISABLE = 3 V | 6 | |
| Logic high threshold (5 V) | VIH | 2.1 | 2.2 | V | VS+=5 V; Disabled or Bypass engaged | 6 | |
| Logic low threshold (5 V) | VIL | 0.75 | 0.8 | V | VS+=5 V; Enabled or Bypass disengaged | 6 |
CAD (KiCad official)
- Symbol:
THS7373IPWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
ths7373ipwr-etched.step/ths7373ipwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ths7373ipwr.step/ths7373ipwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (55 pp, sha256
1f821299b2fda275, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).