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Ray ths7002cpwp: specified limits as data (metadata.characteristics, 60 rows from the datasheet) 739bb11 23d ago

THS7002CPWP

Texas Instruments · Special Purpose Amplifiers · HTSSOP-28-EP

THS7002CPWP from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	GND-A	power_in	Ground connection for channel A (preamp and PGA); the datasheet supports a ±4.5 V to ±16 V dual supply.
2	PGA-A REF	input	Reference input of the channel A programmable gain amplifier, as shown in the THS7002 block diagram; the datasheet gives no further limits for this pin.
3	PGA-A IN−	input	Inverting input of the channel A PGA, which is an inverting programmable gain amplifier with −22 dB to 20 dB gain/attenuation range.
4	PREAMP OUT A	output	Output of the channel A voltage-feedback preamp, accessible for external gain setting and filtering between the preamp and the PGA.
5	PREAMP-A IN−	input	Inverting input of the channel A voltage-feedback preamp, which has a minimum gain of 2 or −1.
6	PREAMP-A IN+	input	Non-inverting input of the channel A voltage-feedback preamp, which has a minimum gain of 2 or −1.
7	PREAMP VCC−	power_in	Negative supply pin for the preamp, within the ±4.5 V to ±16 V supply range.
8	PREAMP VCC+	power_in	Positive supply pin for the preamp, within the ±4.5 V to ±16 V supply range.
9	PREAMP-B IN+	input	Non-inverting input of the channel B voltage-feedback preamp, which has a minimum gain of 2 or −1.
10	PREAMP-B IN−	input	Inverting input of the channel B voltage-feedback preamp, which has a minimum gain of 2 or −1.
11	PREAMP OUT B	output	Output of the channel B voltage-feedback preamp, accessible for external gain setting and filtering between the preamp and the PGA.
12	PGA-B IN−	input	Inverting input of the channel B PGA, which is an inverting programmable gain amplifier with −22 dB to 20 dB gain/attenuation range.
13	PGA-B REF	input	Reference input of the channel B programmable gain amplifier, as shown in the THS7002 block diagram; the datasheet gives no further limits for this pin.
14	GND-B	power_in	Ground connection for channel B (preamp and PGA); the datasheet supports a ±4.5 V to ±16 V dual supply.
15	G0-B	input	Least-significant TTL-compatible gain-select bit for the channel B PGA, one of three bits encoding eight gain levels.
16	G1-B	input	Middle TTL-compatible gain-select bit for the channel B PGA, one of three bits encoding eight gain levels.
17	G2-B	input	Most-significant TTL-compatible gain-select bit for the channel B PGA, one of three bits encoding eight gain levels.
18	SHDN−B	input	Independent shutdown control for channel B, provided for power conservation and multiplexing.
19	PGA-B OUT	output	Output of the channel B programmable gain amplifier, which includes high and low output clamp protection.
20	CLAMP+ (VH)	input	Positive output clamp level (VH) shared by both PGA channels, which limits the output from swinging above the ADC common-mode input range.
21	PGA VCC+	power_in	Positive supply pin for the PGA stages, within the ±4.5 V to ±16 V supply range.
22	PGA VCC−	power_in	Negative supply pin for the PGA stages, within the ±4.5 V to ±16 V supply range.
23	CLAMP− (VL)	input	Negative output clamp level (VL) shared by both PGA channels, which limits the output from swinging below the ADC common-mode input range.
24	PGA-A OUT	output	Output of the channel A programmable gain amplifier, which includes high and low output clamp protection.
25	SHDN−A	input	Independent shutdown control for channel A, provided for power conservation and multiplexing.
26	G2-A	input	Most-significant TTL-compatible gain-select bit for the channel A PGA, one of three bits encoding eight gain levels.
27	G1-A	input	Middle TTL-compatible gain-select bit for the channel A PGA, one of three bits encoding eight gain levels.
28	G0-A	input	Least-significant TTL-compatible gain-select bit for the channel A PGA, one of three bits encoding eight gain levels.
29	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HTSSOP-28-EP
Category	Operational Amplifier/Comparator
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage, VCC (split supply)	VCC	-16.5		16.5	V		4
Output current, IO (preamp)	IO			150	mA		4
Output current, IO (PGA)	IO			85	mA		4
Differential input voltage	VID	-4		4	V		4
Total continuous power dissipation				4.48	W	TA = 25°C, THS7002	4
Maximum junction temperature	TJ			150	°C		4
Storage temperature	Tstg	-65		125	°C		4
Lead temperature				300	°C	1.6 mm from case, 10 s	4
Preamp supply voltage, VCC+ and VCC-	VCC	4.5		16	V	Split supply	4
PGA supply voltage, VCC+ and VCC-	VCC	4.5		16	V	Split supply	4
Operating free-air temperature, C-suffix	TA	0		70	°C	C-suffix	4
Maximum output voltage swing	VOM	3.6	3.8		V	RL = 1 kΩ, VCC = ±5 V	5
Maximum output voltage swing	VOM	13	13.6		V	RL = 1 kΩ, VCC = ±15 V	5
Maximum output voltage swing	VOM	3.5	3.7		V	RL = 150 Ω, VCC = ±5 V	5
Maximum output voltage swing	VOM	11	12.6		V	RL = 250 Ω, VCC = ±15 V	5
Input offset voltage	VIO		1	5	mV	VCC = ±5 V or ±15 V, TA = 25°C	5
Input offset voltage	VIO			7	mV	VCC = ±5 V or ±15 V, TA = full range	5
Common-mode input voltage range	VICR	3.8	4.2		V	VCC = ±5 V	5
Common-mode input voltage range	VICR	13.8	14		V	VCC = ±15 V	5
Output current (preamp)	IO	40	70		mA	RL = 20 Ω, VCC = ±5 V	5
Output current (preamp)	IO	60	95		mA	RL = 20 Ω, VCC = ±15 V	5
Input bias current	IIB		2.5	6	µA	VCC = ±5 V or ±15 V, TA = 25°C	5
Input bias current	IIB			8	µA	VCC = ±5 V or ±15 V, TA = full range	5
Input offset current	IIO		30	175	nA	VCC = ±5 V or ±15 V, TA = 25°C	5
Input offset current	IIO			400	nA	VCC = ±5 V or ±15 V, TA = full range	5
Common-mode rejection ratio	CMRR	80	89		dB	VCC = ±5 V, TA = 25°C	5
Common-mode rejection ratio	CMRR	80	88		dB	VCC = ±15 V, TA = 25°C	5
Power supply rejection ratio	PSRR	85	100		dB	VCC = ±5 V or ±15 V, TA = 25°C	5
Power supply rejection ratio	PSRR	80			dB	VCC = ±5 V or ±15 V, TA = full range	5
Quiescent current (per channel)	ICC		5.5	7	mA	VCC = ±5 V, TA = 25°C	5
Quiescent current (per channel)	ICC			8	mA	VCC = ±5 V, TA = full range	5
Quiescent current (per channel)	ICC		7	8	mA	VCC = ±15 V, TA = 25°C	5
Quiescent current (per channel)	ICC			9	mA	VCC = ±15 V, TA = full range	5
Standby current, disabled preamp	ICC(standby)		0.2	0.3	mA	VCC = ±5 V	6
Standby current, disabled preamp (per channel)	ICC(standby)		0.65	0.8	mA	VI(SHDN) = 2.5 V, VCC = ±15 V	6
Shutdown voltage for power up	VIH(SHDN)	0.8			V	VCC = ±5 V or ±15 V, relative to GND	6
Shutdown voltage for power down	VIL(SHDN)			2	V	VCC = ±5 V or ±15 V, relative to GND	6
Shutdown input current high	IIH(SHDN)		300	400	µA	VCC = ±5 V or ±15 V, VI(SHDN) = 5 V	6
Shutdown input current low	IIL(SHDN)		25	50	µA	VCC = ±5 V or ±15 V, VI(SHDN) = 0.5 V	6
Maximum output voltage swing (PGA)	VOM	3.6	4.1		V	RL = 1 kΩ, VCC = ±5 V	7
Maximum output voltage swing (PGA)	VOM	13.2	13.8		V	RL = 1 kΩ, VCC = ±15 V	7
Input offset voltage (PGA)	VIO		2	9	mV	VCC = ±5 V or ±15 V, TA = 25°C	7
Input offset voltage (PGA)	VIO			11	mV	VCC = ±5 V or ±15 V, TA = full range	7
Reference input voltage range		3.8	4		V	VCC = ±5 V	7
Reference input voltage range		13.5	13.8		V	VCC = ±15 V	7
Input bias current (reference terminal)	IIB		1	2	µA	VCC = ±5 V or ±15 V, TA = 25°C	7
Output current (PGA)	IO	30	50		mA	RL = 20 Ω, VCC = ±5 V	7
Power supply rejection ratio (PGA)	PSRR	75	82		dB	VCC = ±5 V or ±15 V, TA = 25°C	7
Quiescent supply current (PGA, per channel)	ICC		4.8	6	mA	VCC = ±5 V, TA = 25°C	7
Quiescent supply current (PGA, per channel)	ICC		5	7	mA	VCC = ±15 V, TA = 25°C	7
Clamp accuracy			250	300	mV	VCC = ±15 V, VI = ±10 V, VH = 10 V, VL = −10 V, TA = 25°C	7
High-level input voltage (digital gain control)	VIH	2			V	Relative to GND	8
Low-level input voltage (digital gain control)	VIL			0.8	V	Relative to GND	8
Gain accuracy		-7.5	0	7.5	%	Gain = −22 dB to 20 dB, all 8 steps, TA = 25°C	8
Gain accuracy		-8.5		8.5	%	All 8 steps, VCC = ±5 V or ±15 V, TA = full range	8
Channel-to-channel gain accuracy (THS7002 only)		-5.5	0	5.5	%	Gain = −22 dB to 20 dB, all 8 steps, TA = 25°C	8
Channel-to-channel gain accuracy (THS7002 only)		-6.5		6.5	%	All 8 steps, VCC = ±5 V or ±15 V, TA = full range	8
Junction-to-case thermal resistance	θJC		0.72		°C/W	THS7002	30
Junction-to-ambient thermal resistance	θJA		27.9		°C/W	2 oz. trace and copper pad with solder, PCB 3 in x 3 in, no airflow	30
Junction-to-ambient thermal resistance	θJA		56.2		°C/W	2 oz. trace and copper pad without solder, PCB 3 in x 3 in, no airflow	30

CAD (KiCad official)

Symbol: THS7002CPWP
Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
3D model files: ths7002cpwp-etched.step / ths7002cpwp-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ths7002cpwp.step / ths7002cpwp.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (37 pp, sha256 6a2c9ef5bee79d0e, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# THS7002CPWP

**Texas Instruments** · Special Purpose Amplifiers · HTSSOP-28-EP

THS7002CPWP from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND-A | power_in | Ground connection for channel A (preamp and PGA); the datasheet supports a ±4.5 V to ±16 V dual supply. |
| 2 | PGA-A REF | input | Reference input of the channel A programmable gain amplifier, as shown in the THS7002 block diagram; the datasheet gives no further limits for this pin. |
| 3 | PGA-A IN− | input | Inverting input of the channel A PGA, which is an inverting programmable gain amplifier with −22 dB to 20 dB gain/attenuation range. |
| 4 | PREAMP OUT A | output | Output of the channel A voltage-feedback preamp, accessible for external gain setting and filtering between the preamp and the PGA. |
| 5 | PREAMP-A IN− | input | Inverting input of the channel A voltage-feedback preamp, which has a minimum gain of 2 or −1. |
| 6 | PREAMP-A IN+ | input | Non-inverting input of the channel A voltage-feedback preamp, which has a minimum gain of 2 or −1. |
| 7 | PREAMP VCC− | power_in | Negative supply pin for the preamp, within the ±4.5 V to ±16 V supply range. |
| 8 | PREAMP VCC+ | power_in | Positive supply pin for the preamp, within the ±4.5 V to ±16 V supply range. |
| 9 | PREAMP-B IN+ | input | Non-inverting input of the channel B voltage-feedback preamp, which has a minimum gain of 2 or −1. |
| 10 | PREAMP-B IN− | input | Inverting input of the channel B voltage-feedback preamp, which has a minimum gain of 2 or −1. |
| 11 | PREAMP OUT B | output | Output of the channel B voltage-feedback preamp, accessible for external gain setting and filtering between the preamp and the PGA. |
| 12 | PGA-B IN− | input | Inverting input of the channel B PGA, which is an inverting programmable gain amplifier with −22 dB to 20 dB gain/attenuation range. |
| 13 | PGA-B REF | input | Reference input of the channel B programmable gain amplifier, as shown in the THS7002 block diagram; the datasheet gives no further limits for this pin. |
| 14 | GND-B | power_in | Ground connection for channel B (preamp and PGA); the datasheet supports a ±4.5 V to ±16 V dual supply. |
| 15 | G0-B | input | Least-significant TTL-compatible gain-select bit for the channel B PGA, one of three bits encoding eight gain levels. |
| 16 | G1-B | input | Middle TTL-compatible gain-select bit for the channel B PGA, one of three bits encoding eight gain levels. |
| 17 | G2-B | input | Most-significant TTL-compatible gain-select bit for the channel B PGA, one of three bits encoding eight gain levels. |
| 18 | SHDN−B | input | Independent shutdown control for channel B, provided for power conservation and multiplexing. |
| 19 | PGA-B OUT | output | Output of the channel B programmable gain amplifier, which includes high and low output clamp protection. |
| 20 | CLAMP+ (VH) | input | Positive output clamp level (VH) shared by both PGA channels, which limits the output from swinging above the ADC common-mode input range. |
| 21 | PGA VCC+ | power_in | Positive supply pin for the PGA stages, within the ±4.5 V to ±16 V supply range. |
| 22 | PGA VCC− | power_in | Negative supply pin for the PGA stages, within the ±4.5 V to ±16 V supply range. |
| 23 | CLAMP− (VL) | input | Negative output clamp level (VL) shared by both PGA channels, which limits the output from swinging below the ADC common-mode input range. |
| 24 | PGA-A OUT | output | Output of the channel A programmable gain amplifier, which includes high and low output clamp protection. |
| 25 | SHDN−A | input | Independent shutdown control for channel A, provided for power conservation and multiplexing. |
| 26 | G2-A | input | Most-significant TTL-compatible gain-select bit for the channel A PGA, one of three bits encoding eight gain levels. |
| 27 | G1-A | input | Middle TTL-compatible gain-select bit for the channel A PGA, one of three bits encoding eight gain levels. |
| 28 | G0-A | input | Least-significant TTL-compatible gain-select bit for the channel A PGA, one of three bits encoding eight gain levels. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-28-EP |
| Category | Operational Amplifier/Comparator |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage, VCC (split supply) | VCC | -16.5 |  | 16.5 | V |  | 4 |
| Output current, IO (preamp) | IO |  |  | 150 | mA |  | 4 |
| Output current, IO (PGA) | IO |  |  | 85 | mA |  | 4 |
| Differential input voltage | VID | -4 |  | 4 | V |  | 4 |
| Total continuous power dissipation |  |  |  | 4.48 | W | TA = 25°C, THS7002 | 4 |
| Maximum junction temperature | TJ |  |  | 150 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 125 | °C |  | 4 |
| Lead temperature |  |  |  | 300 | °C | 1.6 mm from case, 10 s | 4 |
| Preamp supply voltage, VCC+ and VCC- | VCC | 4.5 |  | 16 | V | Split supply | 4 |
| PGA supply voltage, VCC+ and VCC- | VCC | 4.5 |  | 16 | V | Split supply | 4 |
| Operating free-air temperature, C-suffix | TA | 0 |  | 70 | °C | C-suffix | 4 |
| Maximum output voltage swing | VOM | 3.6 | 3.8 |  | V | RL = 1 kΩ, VCC = ±5 V | 5 |
| Maximum output voltage swing | VOM | 13 | 13.6 |  | V | RL = 1 kΩ, VCC = ±15 V | 5 |
| Maximum output voltage swing | VOM | 3.5 | 3.7 |  | V | RL = 150 Ω, VCC = ±5 V | 5 |
| Maximum output voltage swing | VOM | 11 | 12.6 |  | V | RL = 250 Ω, VCC = ±15 V | 5 |
| Input offset voltage | VIO |  | 1 | 5 | mV | VCC = ±5 V or ±15 V, TA = 25°C | 5 |
| Input offset voltage | VIO |  |  | 7 | mV | VCC = ±5 V or ±15 V, TA = full range | 5 |
| Common-mode input voltage range | VICR | 3.8 | 4.2 |  | V | VCC = ±5 V | 5 |
| Common-mode input voltage range | VICR | 13.8 | 14 |  | V | VCC = ±15 V | 5 |
| Output current (preamp) | IO | 40 | 70 |  | mA | RL = 20 Ω, VCC = ±5 V | 5 |
| Output current (preamp) | IO | 60 | 95 |  | mA | RL = 20 Ω, VCC = ±15 V | 5 |
| Input bias current | IIB |  | 2.5 | 6 | µA | VCC = ±5 V or ±15 V, TA = 25°C | 5 |
| Input bias current | IIB |  |  | 8 | µA | VCC = ±5 V or ±15 V, TA = full range | 5 |
| Input offset current | IIO |  | 30 | 175 | nA | VCC = ±5 V or ±15 V, TA = 25°C | 5 |
| Input offset current | IIO |  |  | 400 | nA | VCC = ±5 V or ±15 V, TA = full range | 5 |
| Common-mode rejection ratio | CMRR | 80 | 89 |  | dB | VCC = ±5 V, TA = 25°C | 5 |
| Common-mode rejection ratio | CMRR | 80 | 88 |  | dB | VCC = ±15 V, TA = 25°C | 5 |
| Power supply rejection ratio | PSRR | 85 | 100 |  | dB | VCC = ±5 V or ±15 V, TA = 25°C | 5 |
| Power supply rejection ratio | PSRR | 80 |  |  | dB | VCC = ±5 V or ±15 V, TA = full range | 5 |
| Quiescent current (per channel) | ICC |  | 5.5 | 7 | mA | VCC = ±5 V, TA = 25°C | 5 |
| Quiescent current (per channel) | ICC |  |  | 8 | mA | VCC = ±5 V, TA = full range | 5 |
| Quiescent current (per channel) | ICC |  | 7 | 8 | mA | VCC = ±15 V, TA = 25°C | 5 |
| Quiescent current (per channel) | ICC |  |  | 9 | mA | VCC = ±15 V, TA = full range | 5 |
| Standby current, disabled preamp | ICC(standby) |  | 0.2 | 0.3 | mA | VCC = ±5 V | 6 |
| Standby current, disabled preamp (per channel) | ICC(standby) |  | 0.65 | 0.8 | mA | VI(SHDN) = 2.5 V, VCC = ±15 V | 6 |
| Shutdown voltage for power up | VIH(SHDN) | 0.8 |  |  | V | VCC = ±5 V or ±15 V, relative to GND | 6 |
| Shutdown voltage for power down | VIL(SHDN) |  |  | 2 | V | VCC = ±5 V or ±15 V, relative to GND | 6 |
| Shutdown input current high | IIH(SHDN) |  | 300 | 400 | µA | VCC = ±5 V or ±15 V, VI(SHDN) = 5 V | 6 |
| Shutdown input current low | IIL(SHDN) |  | 25 | 50 | µA | VCC = ±5 V or ±15 V, VI(SHDN) = 0.5 V | 6 |
| Maximum output voltage swing (PGA) | VOM | 3.6 | 4.1 |  | V | RL = 1 kΩ, VCC = ±5 V | 7 |
| Maximum output voltage swing (PGA) | VOM | 13.2 | 13.8 |  | V | RL = 1 kΩ, VCC = ±15 V | 7 |
| Input offset voltage (PGA) | VIO |  | 2 | 9 | mV | VCC = ±5 V or ±15 V, TA = 25°C | 7 |
| Input offset voltage (PGA) | VIO |  |  | 11 | mV | VCC = ±5 V or ±15 V, TA = full range | 7 |
| Reference input voltage range |  | 3.8 | 4 |  | V | VCC = ±5 V | 7 |
| Reference input voltage range |  | 13.5 | 13.8 |  | V | VCC = ±15 V | 7 |
| Input bias current (reference terminal) | IIB |  | 1 | 2 | µA | VCC = ±5 V or ±15 V, TA = 25°C | 7 |
| Output current (PGA) | IO | 30 | 50 |  | mA | RL = 20 Ω, VCC = ±5 V | 7 |
| Power supply rejection ratio (PGA) | PSRR | 75 | 82 |  | dB | VCC = ±5 V or ±15 V, TA = 25°C | 7 |
| Quiescent supply current (PGA, per channel) | ICC |  | 4.8 | 6 | mA | VCC = ±5 V, TA = 25°C | 7 |
| Quiescent supply current (PGA, per channel) | ICC |  | 5 | 7 | mA | VCC = ±15 V, TA = 25°C | 7 |
| Clamp accuracy |  |  | 250 | 300 | mV | VCC = ±15 V, VI = ±10 V, VH = 10 V, VL = −10 V, TA = 25°C | 7 |
| High-level input voltage (digital gain control) | VIH | 2 |  |  | V | Relative to GND | 8 |
| Low-level input voltage (digital gain control) | VIL |  |  | 0.8 | V | Relative to GND | 8 |
| Gain accuracy |  | -7.5 | 0 | 7.5 | % | Gain = −22 dB to 20 dB, all 8 steps, TA = 25°C | 8 |
| Gain accuracy |  | -8.5 |  | 8.5 | % | All 8 steps, VCC = ±5 V or ±15 V, TA = full range | 8 |
| Channel-to-channel gain accuracy (THS7002 only) |  | -5.5 | 0 | 5.5 | % | Gain = −22 dB to 20 dB, all 8 steps, TA = 25°C | 8 |
| Channel-to-channel gain accuracy (THS7002 only) |  | -6.5 |  | 6.5 | % | All 8 steps, VCC = ±5 V or ±15 V, TA = full range | 8 |
| Junction-to-case thermal resistance | θJC |  | 0.72 |  | °C/W | THS7002 | 30 |
| Junction-to-ambient thermal resistance | θJA |  | 27.9 |  | °C/W | 2 oz. trace and copper pad with solder, PCB 3 in x 3 in, no airflow | 30 |
| Junction-to-ambient thermal resistance | θJA |  | 56.2 |  | °C/W | 2 oz. trace and copper pad without solder, PCB 3 in x 3 in, no airflow | 30 |

## CAD (KiCad official)

- Symbol: `THS7002CPWP`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files: `ths7002cpwp-etched.step` / `ths7002cpwp-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ths7002cpwp.step` / `ths7002cpwp.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ths7001) (37 pp, sha256 `6a2c9ef5bee79d0e`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ths7002cpwp-datasheet.pdf)