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THS4551IRGTT

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Texas Instruments Pre-ordered Chips, VQFN-16-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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THS4551IRGTT

Texas Instruments · Pre-ordered Chips · VQFN-16-EP(3x3)

THS4551IRGTT from Texas Instruments, in a VQFN-16-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 FB- output Inverting (negative) output feedback pin of the THS4551 for RGT package.
2 IN+ input Noninverting (positive) amplifier input.
3 IN- input Inverting (negative) amplifier input.
4 FB+ output Noninverting (positive) output feedback pin.
5 VS+ power_in Positive power-supply input; the datasheet gives a single-supply positive voltage range of 2.7 V to 5.4 V.
6 VS+ power_in Positive power-supply input; the datasheet gives a single-supply positive voltage range of 2.7 V to 5.4 V.
7 VS+ power_in Positive power-supply input; the datasheet gives a single-supply positive voltage range of 2.7 V to 5.4 V.
8 VS+ power_in Positive power-supply input; the datasheet gives a single-supply positive voltage range of 2.7 V to 5.4 V.
9 VOCM input Common-mode voltage input that sets the output common-mode voltage.
10 OUT+ output Noninverting (positive) amplifier output.
11 OUT- output Inverting (negative) amplifier output.
12 PD input Power down: PD logic low puts the device in power-off mode and PD logic high gives normal operation.
13 VS- power_in Negative power-supply input; tie to the negative rail (ground in single-supply use).
14 VS- power_in Negative power-supply input; tie to the negative rail (ground in single-supply use).
15 VS- power_in Negative power-supply input; tie to the negative rail (ground in single-supply use).
16 VS- power_in Negative power-supply input; tie to the negative rail (ground in single-supply use).
17 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-16-EP(3x3)
Category Interface ICs
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (VS+)-(VS-) 5.5 V 6
Supply turn-on/off maximum dV/dT dV/dT -1 1 V/µs 6
Differential input voltage -1 1 V 6
Continuous input current -10 10 mA 6
Continuous output current -20 20 mA 6
Maximum junction temperature TJ 150 °C 6
Operating free-air temperature TA -40 125 °C 6
Storage temperature Tstg -65 150 °C 6
ESD HBM (RGT, any pin to thermal pad) V(ESD) -1000 1000 V RGT package, HBM 6
ESD CDM (RGT) V(ESD) -1250 1250 V RGT package, CDM 6
Single-supply positive voltage VS+ 2.7 5 5.4 V 6
Ambient temperature TA -40 25 125 °C 6
Junction-to-ambient thermal resistance RθJA 54 °C/W RGT (VQFN), 16 pins 6
Junction-to-case (top) thermal resistance RθJC(top) 72 °C/W RGT (VQFN), 16 pins 6
Junction-to-board thermal resistance RθJB 28 °C/W RGT (VQFN), 16 pins 6
Junction-to-top characterization parameter ψJT 3.2 °C/W RGT (VQFN), 16 pins 7
Junction-to-board characterization parameter ψJB 28 °C/W RGT (VQFN), 16 pins 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 12 °C/W RGT (VQFN), 16 pins 7
Open-loop voltage gain AOL 105 125 dB ±3-V differential-to-differential, 1-kΩ load; VS = 5 V 7
Internal feedback trace resistance 3 3.5 4.7 Ω TA = 25°C, RGT only (pins 11-1, 10-4); VS = 5 V 7
Internal feedback trace resistance mismatch -1 0.05 1 Ω TA = 25°C, RGT only (pins 11-1, 10-4); VS = 5 V 7
Input-referred offset voltage VIO -175 50 175 µV TA = 25°C; VS = 5 V 7
Input-referred offset voltage VIO -225 265 µV TA = 0°C to +70°C; VS = 5 V 7
Input-referred offset voltage VIO -295 295 µV TA = -40°C to +85°C; VS = 5 V 7
Input-referred offset voltage VIO -295 375 µV TA = -40°C to +125°C; VS = 5 V 7
Input offset voltage drift -1.8 0.4 1.8 µV/°C TA = -40°C to +125°C (RGT package); VS = 5 V 7
Input bias current IIB 1 1.5 µA TA = 25°C; VS = 5 V 8
Input bias current IIB 1.73 µA TA = 0°C to +70°C; VS = 5 V 8
Input bias current IIB 1.8 µA TA = -40°C to +85°C; VS = 5 V 8
Input bias current IIB 2 µA TA = -40°C to +125°C; VS = 5 V 8
Input bias current drift 2 3.3 5 nA/°C TA = -40°C to +125°C; VS = 5 V 8
Input offset current IOS -50 10 50 nA TA = 25°C; VS = 5 V 8
Input offset current IOS -57 63 nA TA = 0°C to +70°C; VS = 5 V 8
Input offset current IOS -68 67 nA TA = -40°C to +85°C; VS = 5 V 8
Input offset current IOS -68 78 nA TA = -40°C to +125°C; VS = 5 V 8
Input offset current drift -120 20 120 pA/°C TA = -40°C to +125°C (RGT and RUN package); VS = 5 V 8
Common-mode rejection ratio CMRR 93 110 dB Input pins at [(VS+), (VS-)] / 2; VS = 5 V 8
Continuous output current 60 65 mA TA = 25°C, ±2.5 V, RL= 40 Ω, VOCM offset < ±20 mV; VS = 5 V 8
Continuous output current 50 mA TA = -40°C to +125°C, ±2.1 V, RL= 40 Ω, VOCM offset < ±20 mV; VS = 5 V 8
Linear output current 40 45 mA TA = 25°C, ±2.1 V, RL= 50 Ω, AOL > 80 dB; VS = 5 V 8
Linear output current 30 mA TA = -40°C to +125°C, ±1.6 V, RL= 50 Ω, AOL > 80 dB; VS = 5 V 8
Specified operating voltage 2.7 5 5.4 V 8
Quiescent operating current IQ 1.28 1.37 1.44 mA TA ≈ 25°C, VS+ = 5 V 8
Quiescent operating current IQ 0.97 1.92 mA TA = -40°C to +125°C, VS+ = 5 V 8
Quiescent current temperature coefficient dIQ/dT 2.4 3.9 5.4 µA/°C VS+ = 5 V 8
Power-supply rejection ratio ±PSRR 93 110 dB Either supply pin to differential VOUT; VS = 5 V 8
Disable pin bias current -100 10 100 nA PD = VS- → VS+ 8
Power-down quiescent current IQ(PD) -2 1 5 µA 9
VOCM gain 0.997 0.999 1.001 V/V VOCM control pin input to output average voltage 10
VOCM input bias current -100 10 100 nA 10
Default voltage offset from [(VS+), (VS-)] / 2 -12 2 12 mV VOCM pin open 10
Common-mode offset voltage CM VOS -5 1 5 mV VOCM pin driven to [(VS+), (VS-)] / 2, TA = 25°C 10
Common-mode offset voltage CM VOS -5.25 5.5 mV VOCM pin driven to [(VS+), (VS-)] / 2, TA = 0°C to +70°C 10
Common-mode offset voltage CM VOS -5.7 5.6 mV VOCM pin driven to [(VS+), (VS-)] / 2, TA = -40°C to +85°C 10
Common-mode offset voltage CM VOS -5.7 6 mV VOCM pin driven to [(VS+), (VS-)] / 2, TA = -40°C to +125°C 10
Common-mode offset voltage drift -10 2 10 µV/°C TA = -40°C to +125°C 10
Common-mode loop supply headroom to negative supply 0.7 V < ±15-mV shift from midsupply CM VOS, TA = -40°C to +125°C 10
Common-mode loop supply headroom to positive supply 1.3 V < ±15-mV shift from midsupply CM VOS, TA = -40°C to +125°C 10

CAD (KiCad official)

  • Symbol: THS4551IRGTT
  • Footprint: Package_DFN_QFN:QFN-16-1EP_3x3mm_P0.5mm_EP1.7x1.7mm
  • 3D model: VQFN-16-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: ths4551irgtt-etched.step / ths4551irgtt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ths4551irgtt.step / ths4551irgtt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (82 pp, sha256 f1d7ab87169a4112, retrieved 2026-10-31, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF