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Ray ths4271mdgnrep: specified limits as data (metadata.characteristics, 58 rows from the datasheet) 903074e 13d ago

THS4271MDGNREP

Texas Instruments · Operational Amplifier · HVSSOP-8-EP

THS4271MDGNREP from Texas Instruments, in a HVSSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No internal connection.
2 IN− input Inverting input; input voltage must not exceed ±VS (absolute maximum) and the common-mode input range is VS- + 1.4 V to VS+ - 1.4 V.
3 IN+ input Non-inverting input; input voltage must not exceed ±VS (absolute maximum) and the common-mode input range is VS- + 1.4 V to VS+ - 1.4 V.
4 VS- power_in Negative supply rail; dual supply ±2.5 V to ±5 V or single supply 5 V to 10 V recommended, with 16.5 V absolute maximum total supply voltage.
5 NC unconnected No internal connection.
6 VOUT output Amplifier output; output current is limited to 100 mA absolute maximum.
7 VS+ power_in Positive supply rail; dual supply ±2.5 V to ±5 V or single supply 5 V to 10 V recommended, with 16.5 V absolute maximum total supply voltage.
8 NC unconnected No internal connection.
9 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HVSSOP-8-EP
Category Amplifiers/Comparators
Pins 9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Open-loop voltage gain (AOL) AOL 65 75 dB VS = ±5 V; VO = ± 50 mV, RL = 499 Ω; +25°C 5
Open-loop voltage gain (AOL) AOL 56 dB VS = ±5 V; VO = ± 50 mV, RL = 499 Ω; –55°C to +125°C 5
Input offset voltage 5 14 mV VS = ±5 V; VCM = 0 V; +25°C 5
Input offset voltage 16 mV VS = ±5 V; VCM = 0 V; –55°C to +125°C 5
Common-mode input range 3.6 4 V VS = ±5 V; +25°C 5
Common-mode input range 3.5 V VS = ±5 V; –55°C to +125°C 5
Common-mode rejection ratio 67 72 dB VS = ±5 V; VCM = ± 2 V; +25°C 5
Common-mode rejection ratio 62 dB VS = ±5 V; VCM = ± 2 V; –55°C to +125°C 5
Power-supply rejection (+PSRR) +PSRR 75 85 dB VS+ = 5.5 V to 4.5 V, VS– = 5 V; +25°C 6
Power-supply rejection (+PSRR) +PSRR 58 dB VS+ = 5.5 V to 4.5 V, VS– = 5 V; –55°C to +125°C 6
Power-supply rejection (-PSRR) -PSRR 65 75 dB VS+ = 5 V, VS– = -5.5 V to -4.5 V; +25°C 6
Power-supply rejection (-PSRR) -PSRR 57 dB VS+ = 5 V, VS– = -5.5 V to -4.5 V; –55°C to +125°C 6
Output voltage swing 3.75 4 V VS = ±5 V; G = +2; +25°C 6
Output voltage swing 3.6 V VS = ±5 V; G = +2; –55°C to +125°C 6
Output current (sourcing) 120 160 mA VS = ±5 V; RL = 10 Ω; +25°C 6
Output current (sourcing) 104 mA VS = ±5 V; RL = 10 Ω; –55°C to +125°C 6
Output current (sinking) 60 80 mA VS = ±5 V; RL = 10 Ω; +25°C 6
Output current (sinking) 44 mA VS = ±5 V; RL = 10 Ω; –55°C to +125°C 6
Maximum quiescent current 22 24 mA VS = ±5 V; +25°C 6
Maximum quiescent current 34 mA VS = ±5 V; –55°C to +125°C 6
Minimum quiescent current 20 22 mA VS = ±5 V; +25°C 6
Minimum quiescent current 13 mA VS = ±5 V; –55°C to +125°C 6
Open-loop voltage gain (AOL) AOL 63 68 dB VS = 5 V; VO = ± 50 mV, RL = 499 Ω; +25°C 7
Open-loop voltage gain (AOL) AOL 56 dB VS = 5 V; VO = ± 50 mV, RL = 499 Ω; –55°C to +125°C 7
Input offset voltage 5 14 mV VS = 5 V; VCM = VS/2; +25°C 7
Input offset voltage 16 mV VS = 5 V; VCM = VS/2; –55°C to +125°C 7
Common-mode input range 1.3 3.7 V VS = 5 V; +25°C 7
Common-mode input range 1.5 3.5 V VS = 5 V; –55°C to +125°C 7
Common-mode rejection ratio 67 72 dB VS = 5 V; VCM = ± 0.5 V, VO = 2.5 V; +25°C 7
Common-mode rejection ratio 62 dB VS = 5 V; VCM = ± 0.5 V, VO = 2.5 V; –55°C to +125°C 7
Output voltage swing 1.4 3.6 V VS = 5 V; G = +2; +25°C 7
Output voltage swing 1.5 3.5 V VS = 5 V; G = +2; –55°C to +125°C 7
Output current (sourcing) 90 120 mA VS = 5 V; RL = 10 Ω; +25°C 7
Output current (sourcing) 78 mA VS = 5 V; RL = 10 Ω; –55°C to +125°C 7
Output current (sinking) 45 65 mA VS = 5 V; RL = 10 Ω; +25°C 7
Output current (sinking) 37 mA VS = 5 V; RL = 10 Ω; –55°C to +125°C 7
Maximum quiescent current 20 23 mA VS = 5 V; +25°C 8
Maximum quiescent current 34 mA VS = 5 V; –55°C to +125°C 8
Minimum quiescent current 18 20 mA VS = 5 V; +25°C 8
Minimum quiescent current 13 mA VS = 5 V; –55°C to +125°C 8
Power-supply rejection (+PSRR) +PSRR 70 85 dB VS+ = 5.5 V to 4.5 V, VS– = 0 V; +25°C 8
Power-supply rejection (+PSRR) +PSRR 57 dB VS+ = 5.5 V to 4.5 V, VS– = 0 V; –55°C to +125°C 8
Power-supply rejection (-PSRR) -PSRR 65 75 dB VS+ = 5 V, VS– = –0.5 V to 0.5 V; +25°C 8
Power-supply rejection (-PSRR) -PSRR 56 dB VS+ = 5 V, VS– = –0.5 V to 0.5 V; –55°C to +125°C 8
Supply voltage (VS+ and VS–), dual supply VS+ and VS– 2.5 5 V Dual supply 4
Supply voltage (VS+ and VS–), single supply VS+ and VS– 5 10 V Single supply 4
Supply voltage VS 16.5 V 3
Output current IO 100 mA 3
Maximum junction temperature TJ 150 °C 3
Maximum junction temperature, continuous operation long term reliability TJ 125 °C Continuous operation, long term reliability 3
Maximum junction temperature to prevent oscillation TJ 60 °C Maximum junction temperature to prevent oscillation 3
Storage temperature range Tstg -65 150 °C 3
Lead temperature 300 °C 1,6 mm (1/16 inch) from case for 10 seconds 3
ESD rating HBM 3000 V HBM 3
ESD rating CDM 1000 V CDM 3
ESD rating MM 100 V MM 3
Junction-to-case thermal resistance, DGN (8 pin) θJC 4.7 °C/W JEDEC standard High-K test PCB 3
Junction-to-ambient thermal resistance, DGN (8 pin) θJA 58.4 °C/W JEDEC standard High-K test PCB 3

CAD (KiCad official)

  • Symbol: THS4271MDGNREP
  • Footprint: Package_SO:HVSSOP-8-1EP_3x3mm_P0.65mm_EP1.57x1.89mm
  • 3D model: HVSSOP-8-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal HVSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: ths4271mdgnrep-etched.step / ths4271mdgnrep-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ths4271mdgnrep.step / ths4271mdgnrep.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 79edad241b290916, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF