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Ray ths4222dgnr: specified limits as data (metadata.characteristics, 49 rows from the datasheet) cea5fe4 14d ago

THS4222DGNR

Texas Instruments · Operational Amplifier · HVSSOP-8-EP

THS4222DGNR from Texas Instruments, in a HVSSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	1OUT	output	Channel 1 amplifier output, which swings rail-to-rail (VO = ±4.8 V at RL = 2 kΩ per the Features list).
2	1IN−	input	Channel 1 inverting input; the input common-mode voltage range is VS− + 1.1 V to VS+ − 1.1 V (recommended operating conditions).
3	1IN+	input	Channel 1 non-inverting input; the input common-mode voltage range is VS− + 1.1 V to VS+ − 1.1 V (recommended operating conditions).
4	VS−	power_in	Negative supply rail; recommended supply is 2.7 V to 15 V single supply or ±1.35 V to ±7.5 V dual supply.
5	2IN+	input	Channel 2 non-inverting input; the input common-mode voltage range is VS− + 1.1 V to VS+ − 1.1 V (recommended operating conditions).
6	2IN−	input	Channel 2 inverting input; the input common-mode voltage range is VS− + 1.1 V to VS+ − 1.1 V (recommended operating conditions).
7	2OUT	output	Channel 2 amplifier output, which swings rail-to-rail (VO = ±4.8 V at RL = 2 kΩ per the Features list).
8	VS+	power_in	Positive supply rail; absolute maximum supply voltage is 16.5 V.
9	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	HVSSOP-8-EP
Category	Amplifiers/Comparators
Pins	9

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Slew rate	SR	990			V/µs	G = -1, VO = ±2.5 Vpp, VS = ±5 V, RL = 499 Ω	3
Slew rate	SR	975			V/µs	G = 1, VO = ±2.5 Vpp, VS = ±5 V, RL = 499 Ω	3
Open-loop voltage gain	AOL	80			dB	VO = ±2 V, 25°C	3
Open-loop voltage gain	AOL	75			dB	VO = ±2 V, 0°C to 70°C	3
Input offset voltage	VIO			10	mV	VCM = 0 V, 25°C	3
Input offset voltage	VIO			16	mV	VCM = 0 V, 0°C to 70°C	3
Input bias current	IIB			3	µA	VCM = 0 V, 25°C	3
Input bias current	IIB			5	µA	VCM = 0 V, 0°C to 70°C	3
Input offset current	IIO			500	nA	VCM = 0 V, 25°C	3
Input offset current	IIO			700	nA	VCM = 0 V, 0°C to 70°C	3
Common-mode input range	VICR	-4		4	V	25°C	3
Common-mode input range	VICR	-3.9		3.9	V	over temperature column as printed	3
Common-mode rejection ratio	CMRR	74			dB	VCM = ±2 V, 25°C	3
Common-mode rejection ratio	CMRR	69			dB	VCM = ±2 V, 0°C to 70°C	3
Input capacitance, common-mode	CIN			1	pF	common-mode	3
Input capacitance, differential	CIN			0.5	pF	differential	3
Output voltage swing	VO	-4.5		4.5	V	RL = 499 Ω, 25°C	4
Output voltage swing	VO	-4.4		4.4	V	RL = 499 Ω, 0°C to 70°C	4
Output voltage swing	VO	-4.8		4.8	V	RL = 2 kΩ	4
Output current (sourcing)	IO	92			mA	RL = 10 Ω, 25°C	4
Output current (sourcing)	IO	88			mA	RL = 10 Ω, 0°C to 70°C	4
Output current (sinking)	IO	-92			mA	RL = 10 Ω, 25°C	4
Output current (sinking)	IO	-88			mA	RL = 10 Ω, 0°C to 70°C	4
Specified operating voltage	VS		5	7.5	V	as printed (±5 V typ; max ±7.5 V over temperature)	4
Maximum quiescent current	IQ		14	18	mA	Per channel, 25°C	4
Maximum quiescent current	IQ			20	mA	Per channel, 0°C to 70°C	4
Maximum quiescent current	IQ			22	mA	Per channel, -40°C to 85°C	4
Power supply rejection (±PSRR)	PSRR	62			dB	25°C	4
Power supply rejection (±PSRR)	PSRR	60			dB	0°C to 70°C	4
Maximum power-down current	IPD		700	900	µA	Per channel, PD ≤ REF+1.0 V, REF = 0 V, 25°C	4
Maximum power-down current	IPD			1000	µA	Per channel, PD ≤ REF+1.0 V, REF = 0 V, 0°C to 70°C	4
Power-down voltage level, enable	REF	1.8			V	Enable at REF+1.8 V min, REF = 0 V or VS−	4
Power-down voltage level, power down	REF			1	V	Power down at REF+1 V max, REF = 0 V or VS−	4
Power-down voltage level, enable	REF	-1			V	Enable at REF−1 V min, REF = VS+ or floating	4
Power-down voltage level, power down	REF			-1.5	V	Power down at REF−1.5 V max, REF = VS+ or floating	4
Supply voltage, VS	VS			16.5	V	over operating free-air temperature range	2
Output current, IO	IO			100	mA		2
Differential input voltage, VID	VID			4	V		2
Maximum junction temperature, TJ	TJ			150	°C		2
Maximum junction temperature, continuous operation	TJ			125	°C	continuous operation, long-term reliability	2
Storage temperature range	Tstg	-65		150	°C		2
Lead temperature	TL			300	°C	1,6 mm (1/16 inch) from case for 10 seconds	2
ESD HBM	ESD			3000	V	HBM, THS4222/6	2
ESD CDM	ESD			1500	V	CDM	2
ESD MM	ESD			200	V	MM, THS4222/6	2
Supply voltage, dual supply (VS+ and VS−)	VS	1.35		7.5	V	dual supply, ±VS	2
Supply voltage, single supply	VS	2.7		15	V	single supply	2
Thermal resistance, junction to ambient, DGN	θJA		58.4		°C/W	DGN (8), JEDEC High-K test PCB	2
Thermal resistance, junction to case, DGN	θJC		4.7		°C/W	DGN (8)	2

CAD (KiCad official)

Symbol: THS4222DGNR
Footprint: Package_SO:HVSSOP-8-1EP_3x3mm_P0.65mm_EP1.57x1.89mm
3D model: HVSSOP-8-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal HVSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
3D model files: ths4222dgnr-etched.step / ths4222dgnr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ths4222dgnr.step / ths4222dgnr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (49 pp, sha256 f50c774974bf2804, retrieved 2026-10-11, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# THS4222DGNR

**Texas Instruments** · Operational Amplifier · HVSSOP-8-EP

THS4222DGNR from Texas Instruments, in a HVSSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1OUT | output | Channel 1 amplifier output, which swings rail-to-rail (VO = ±4.8 V at RL = 2 kΩ per the Features list). |
| 2 | 1IN− | input | Channel 1 inverting input; the input common-mode voltage range is VS− + 1.1 V to VS+ − 1.1 V (recommended operating conditions). |
| 3 | 1IN+ | input | Channel 1 non-inverting input; the input common-mode voltage range is VS− + 1.1 V to VS+ − 1.1 V (recommended operating conditions). |
| 4 | VS− | power_in | Negative supply rail; recommended supply is 2.7 V to 15 V single supply or ±1.35 V to ±7.5 V dual supply. |
| 5 | 2IN+ | input | Channel 2 non-inverting input; the input common-mode voltage range is VS− + 1.1 V to VS+ − 1.1 V (recommended operating conditions). |
| 6 | 2IN− | input | Channel 2 inverting input; the input common-mode voltage range is VS− + 1.1 V to VS+ − 1.1 V (recommended operating conditions). |
| 7 | 2OUT | output | Channel 2 amplifier output, which swings rail-to-rail (VO = ±4.8 V at RL = 2 kΩ per the Features list). |
| 8 | VS+ | power_in | Positive supply rail; absolute maximum supply voltage is 16.5 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HVSSOP-8-EP |
| Category | Amplifiers/Comparators |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Slew rate | SR | 990 |  |  | V/µs | G = -1, VO = ±2.5 Vpp, VS = ±5 V, RL = 499 Ω | 3 |
| Slew rate | SR | 975 |  |  | V/µs | G = 1, VO = ±2.5 Vpp, VS = ±5 V, RL = 499 Ω | 3 |
| Open-loop voltage gain | AOL | 80 |  |  | dB | VO = ±2 V, 25°C | 3 |
| Open-loop voltage gain | AOL | 75 |  |  | dB | VO = ±2 V, 0°C to 70°C | 3 |
| Input offset voltage | VIO |  |  | 10 | mV | VCM = 0 V, 25°C | 3 |
| Input offset voltage | VIO |  |  | 16 | mV | VCM = 0 V, 0°C to 70°C | 3 |
| Input bias current | IIB |  |  | 3 | µA | VCM = 0 V, 25°C | 3 |
| Input bias current | IIB |  |  | 5 | µA | VCM = 0 V, 0°C to 70°C | 3 |
| Input offset current | IIO |  |  | 500 | nA | VCM = 0 V, 25°C | 3 |
| Input offset current | IIO |  |  | 700 | nA | VCM = 0 V, 0°C to 70°C | 3 |
| Common-mode input range | VICR | -4 |  | 4 | V | 25°C | 3 |
| Common-mode input range | VICR | -3.9 |  | 3.9 | V | over temperature column as printed | 3 |
| Common-mode rejection ratio | CMRR | 74 |  |  | dB | VCM = ±2 V, 25°C | 3 |
| Common-mode rejection ratio | CMRR | 69 |  |  | dB | VCM = ±2 V, 0°C to 70°C | 3 |
| Input capacitance, common-mode | CIN |  |  | 1 | pF | common-mode | 3 |
| Input capacitance, differential | CIN |  |  | 0.5 | pF | differential | 3 |
| Output voltage swing | VO | -4.5 |  | 4.5 | V | RL = 499 Ω, 25°C | 4 |
| Output voltage swing | VO | -4.4 |  | 4.4 | V | RL = 499 Ω, 0°C to 70°C | 4 |
| Output voltage swing | VO | -4.8 |  | 4.8 | V | RL = 2 kΩ | 4 |
| Output current (sourcing) | IO | 92 |  |  | mA | RL = 10 Ω, 25°C | 4 |
| Output current (sourcing) | IO | 88 |  |  | mA | RL = 10 Ω, 0°C to 70°C | 4 |
| Output current (sinking) | IO | -92 |  |  | mA | RL = 10 Ω, 25°C | 4 |
| Output current (sinking) | IO | -88 |  |  | mA | RL = 10 Ω, 0°C to 70°C | 4 |
| Specified operating voltage | VS |  | 5 | 7.5 | V | as printed (±5 V typ; max ±7.5 V over temperature) | 4 |
| Maximum quiescent current | IQ |  | 14 | 18 | mA | Per channel, 25°C | 4 |
| Maximum quiescent current | IQ |  |  | 20 | mA | Per channel, 0°C to 70°C | 4 |
| Maximum quiescent current | IQ |  |  | 22 | mA | Per channel, -40°C to 85°C | 4 |
| Power supply rejection (±PSRR) | PSRR | 62 |  |  | dB | 25°C | 4 |
| Power supply rejection (±PSRR) | PSRR | 60 |  |  | dB | 0°C to 70°C | 4 |
| Maximum power-down current | IPD |  | 700 | 900 | µA | Per channel, PD ≤ REF+1.0 V, REF = 0 V, 25°C | 4 |
| Maximum power-down current | IPD |  |  | 1000 | µA | Per channel, PD ≤ REF+1.0 V, REF = 0 V, 0°C to 70°C | 4 |
| Power-down voltage level, enable | REF | 1.8 |  |  | V | Enable at REF+1.8 V min, REF = 0 V or VS− | 4 |
| Power-down voltage level, power down | REF |  |  | 1 | V | Power down at REF+1 V max, REF = 0 V or VS− | 4 |
| Power-down voltage level, enable | REF | -1 |  |  | V | Enable at REF−1 V min, REF = VS+ or floating | 4 |
| Power-down voltage level, power down | REF |  |  | -1.5 | V | Power down at REF−1.5 V max, REF = VS+ or floating | 4 |
| Supply voltage, VS | VS |  |  | 16.5 | V | over operating free-air temperature range | 2 |
| Output current, IO | IO |  |  | 100 | mA |  | 2 |
| Differential input voltage, VID | VID |  |  | 4 | V |  | 2 |
| Maximum junction temperature, TJ | TJ |  |  | 150 | °C |  | 2 |
| Maximum junction temperature, continuous operation | TJ |  |  | 125 | °C | continuous operation, long-term reliability | 2 |
| Storage temperature range | Tstg | -65 |  | 150 | °C |  | 2 |
| Lead temperature | TL |  |  | 300 | °C | 1,6 mm (1/16 inch) from case for 10 seconds | 2 |
| ESD HBM | ESD |  |  | 3000 | V | HBM, THS4222/6 | 2 |
| ESD CDM | ESD |  |  | 1500 | V | CDM | 2 |
| ESD MM | ESD |  |  | 200 | V | MM, THS4222/6 | 2 |
| Supply voltage, dual supply (VS+ and VS−) | VS | 1.35 |  | 7.5 | V | dual supply, ±VS | 2 |
| Supply voltage, single supply | VS | 2.7 |  | 15 | V | single supply | 2 |
| Thermal resistance, junction to ambient, DGN | θJA |  | 58.4 |  | °C/W | DGN (8), JEDEC High-K test PCB | 2 |
| Thermal resistance, junction to case, DGN | θJC |  | 4.7 |  | °C/W | DGN (8) | 2 |

## CAD (KiCad official)

- Symbol: `THS4222DGNR`
- Footprint: `Package_SO:HVSSOP-8-1EP_3x3mm_P0.65mm_EP1.57x1.89mm`
- 3D model: HVSSOP-8-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.0 mm nominal HVSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `ths4222dgnr-etched.step` / `ths4222dgnr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ths4222dgnr.step` / `ths4222dgnr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/ths4221) (49 pp, sha256 `f50c774974bf2804`, retrieved 2026-10-11, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ths4222dgnr-datasheet.pdf)