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THCV236-NNTA

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THine Elec Video Interface ICs, QFN-64-EP(9x9). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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THCV236-NNTA

THine Elec · Video Interface ICs · QFN-64-EP(9x9)

THCV236-NNTA from THine Elec, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PDN0 input Main-Link Power Down (LVCMOS, low-speed). 0 = Main-Link power down; 1 = Main-Link normal operation.
2 PDN1 input Sub-Link Power Down (LVCMOS, low-speed). 0 = Sub-Link power down, Main-Link setting via external pins; 1 = Sub-Link normal operation, Main-Link setting via 2-wire serial I/F.
3 LFSEL input Low Frequency mode select (LVCMOS input). 0 = Low Frequency mode disabled; 1 = Low Frequency mode enabled.
4 TEST1 input Factory test pin (LVCMOS low-speed input). Must be tied to GND for normal operation.
5 TEST2 input Factory test pin (LVCMOS input). Must be tied to GND for normal operation.
6 RF/BETOUT bidirectional Dual-function LVCMOS I/O. RF: Output clock triggering edge select (0 = falling, 1 = rising). BETOUT: Field BET result output when Field BET mode is active.
7 COL0/INT/GPIO2 bidirectional Multi-function LVCMOS I/O. COL0: Data width setting when PDN1=0. INT: Sub-Link interrupt output when SUBMODE=0 and Sub-Link is Master (open-drain, needs pull-up to VDD; L = interrupt, H = idle). GPIO2: General purpose I/O when SUBMODE=0 and MSSEL=1.
8 COL1/SD0 bidirectional Multi-function LVCMOS I/O. COL1: Color Space Converter enable / data width setting when PDN1=0. SD0: When SUBMODE=0 acts as SDA of the 2-wire serial I/F (needs pull-up to VDD); when SUBMODE=1 acts as Sub-Link data input (MSSEL=0) or output (MSSEL=1) for Low Speed Data Bridge Mode.
9 OUTSEL/SD1 bidirectional Multi-function LVCMOS I/O. OUTSEL: Permanent Clock Output enable when PDN1=0 (0 = disabled, 1 = enabled). SD1: When SUBMODE=0 acts as SCL of the 2-wire serial I/F (needs pull-up to VDD); when SUBMODE=1 acts as Sub-Link data I/O for Low Speed Data Bridge Mode.
10 TTLDRV/SD2/AIN0/GPIO1 bidirectional Multi-function LVCMOS I/O. TTLDRV: TTL output drive strength select when PDN1=0 (0 = weak, 1 = normal). SD2: Sub-Link data I/O in Low Speed Data Bridge mode. AIN0: Device ID setting bit for 2-wire serial I/F when SUBMODE=0 and MSSEL=0 (see Table 26). GPIO1: General purpose I/O when SUBMODE=0 and MSSEL=1 (open-drain requires pull-up to VDD).
11 LATEN/SD3/AIN1/GPIO0 bidirectional Multi-function LVCMOS I/O. LATEN: Latch select input for Field BET (0 = not latched, 1 = latched). SD3: Sub-Link data I/O in Low Speed Data Bridge mode. AIN1: Device ID setting bit for 2-wire serial I/F when SUBMODE=0 and MSSEL=0. GPIO0: General purpose I/O when SUBMODE=0 and MSSEL=1 (open-drain requires pull-up to VDD).
12 D31 output LVCMOS pixel data output bit 31 (Main-Link recovered data).
13 D30 output LVCMOS pixel data output bit 30 (Main-Link recovered data).
14 D29 output LVCMOS pixel data output bit 29 (Main-Link recovered data).
15 D28 output LVCMOS pixel data output bit 28 (Main-Link recovered data).
16 VDD power_in 1.7 V - 3.6 V digital power supply pin for LVCMOS I/O.
17 D27 output LVCMOS pixel data output bit 27 (Main-Link recovered data).
18 D26 output LVCMOS pixel data output bit 26 (Main-Link recovered data).
19 D25/GPIO4 bidirectional D25: LVCMOS pixel data output bit 25. GPIO4: General purpose I/O when SUBMODE=0, MSSEL=0 and RXDEFSEL=0 (open-drain needs pull-up to VDD; push-pull needs no external component).
20 D24/GPIO3 bidirectional D24: LVCMOS pixel data output bit 24. GPIO3: General purpose I/O when SUBMODE=0, MSSEL=0 and RXDEFSEL=0 (open-drain needs pull-up to VDD; push-pull needs no external component).
21 D23 output LVCMOS pixel data output bit 23 (Main-Link recovered data).
22 D22 output LVCMOS pixel data output bit 22 (Main-Link recovered data).
23 D21 output LVCMOS pixel data output bit 21 (Main-Link recovered data).
24 D20 output LVCMOS pixel data output bit 20 (Main-Link recovered data).
25 VDD power_in 1.7 V - 3.6 V digital power supply pin for LVCMOS I/O.
26 CLKOUT output Recovered pixel clock output (LVCMOS). Delivers the pixel clock reconstructed from the incoming Main-Link stream.
27 D19 output LVCMOS pixel data output bit 19 (Main-Link recovered data).
28 D18 output LVCMOS pixel data output bit 18 (Main-Link recovered data).
29 D17 output LVCMOS pixel data output bit 17 (Main-Link recovered data).
30 D16 output LVCMOS pixel data output bit 16 (Main-Link recovered data).
31 D15 output LVCMOS pixel data output bit 15 (Main-Link recovered data).
32 VDD power_in 1.7 V - 3.6 V digital power supply pin for LVCMOS I/O.
33 D14 output LVCMOS pixel data output bit 14 (Main-Link recovered data).
34 D13 output LVCMOS pixel data output bit 13 (Main-Link recovered data).
35 D12 output LVCMOS pixel data output bit 12 (Main-Link recovered data).
36 D11 output LVCMOS pixel data output bit 11 (Main-Link recovered data).
37 D10 output LVCMOS pixel data output bit 10 (Main-Link recovered data).
38 D9 output LVCMOS pixel data output bit 9 (Main-Link recovered data).
39 D8 output LVCMOS pixel data output bit 8 (Main-Link recovered data).
40 AVDD power_in 1.7 V - 3.6 V analog power supply pin for the internal LDO. Should be filtered with a series noise filter (e.g. ferrite bead) plus decoupling capacitor.
41 VDD power_in 1.7 V - 3.6 V digital power supply pin for LVCMOS I/O.
42 D7 output LVCMOS pixel data output bit 7 (Main-Link recovered data).
43 D6 output LVCMOS pixel data output bit 6 (Main-Link recovered data).
44 D5 output LVCMOS pixel data output bit 5 (Main-Link recovered data).
45 D4 output LVCMOS pixel data output bit 4 (Main-Link recovered data).
46 D3 output LVCMOS pixel data output bit 3 (Main-Link recovered data).
47 D2 output LVCMOS pixel data output bit 2 (Main-Link recovered data).
48 VSYNC output Vertical sync LVCMOS output recovered from the Main-Link.
49 VDD power_in 1.7 V - 3.6 V digital power supply pin for LVCMOS I/O.
50 HSYNC output Horizontal sync LVCMOS output recovered from the Main-Link.
51 DE output Data Enable LVCMOS output recovered from the Main-Link.
52 D1 output LVCMOS pixel data output bit 1 (Main-Link recovered data).
53 D0 output LVCMOS pixel data output bit 0 (Main-Link recovered data).
54 HTPDN/SUBMODE output Open-drain LVCMOS. HTPDN: Hot Plug Detect output when PDN1=0; must be connected to the transmitter's HTPDN through a 10 kΩ pull-up to VDD. SUBMODE: Sub-Link Mode Select when PDN1=1 (0 = 2-wire serial I/F mode, default no clock stretching; 1 = Low Speed Data Bridge mode). Setting must NOT differ between THCV235 and THCV236.
55 LOCKN/MSSEL output Open-drain LVCMOS. LOCKN: Lock Detect output when PDN1=0; must be connected to the transmitter's LOCKN through a 10 kΩ pull-up to VDD. MSSEL: Sub-Link Master/Slave select when PDN1=1 (0 = Sub-Link Master / inside 2-wire I/F is slave, 1 = Sub-Link Slave / inside 2-wire I/F is master). Setting MUST differ between THCV235 and THCV236 (one Master, one Slave). Sub-Link Master side connects to the host MPU.
56 CAPOUT power_out Decoupling capacitor pin for the internal 1.2 V LDO output. Bypass to GND with 10 µF; may not supply any external load. Must be tied to CAPINA.
57 RXN input High-speed CML signal input (Main-Link), negative side of the differential pair. AC-coupled; carries serialized video data from the THCV235 transmitter at up to 4.00 Gbps.
58 RXP input High-speed CML signal input (Main-Link), positive side of the differential pair. AC-coupled; carries serialized video data from the THCV235 transmitter at up to 4.00 Gbps.
59 CAPINA power_in Reference input for internal analog circuits. Must be tied to CAPOUT and bypassed to GND with 0.1 µF.
60 MAINMODE/RCMN bidirectional MAINMODE: Sets Main-Link mode when PDN1=0 (0 = V-by-One HS Mode, 1 = Sync Free Mode). RCMN: CML bi-directional Sub-Link signal input/output (negative side) when PDN1=1.
61 HFSEL/RCMP bidirectional HFSEL: High Frequency mode select when PDN1=0 (0 = disable, 1 = enable). RCMP: CML bi-directional Sub-Link signal input/output (positive side) when PDN1=1.
62 RXDEFSEL input Internal register default setting select (LVCMOS input). 0 = defaults for THCV231, 1 = defaults for THCV235. See Table 44/45.
63 OE input Output Enable (low-speed LVCMOS input). 0 = LVCMOS outputs disabled (Hi-Z), except HTPDN and LOCKN when PDN1=0 and except BETOUT when BET=1; 1 = LVCMOS outputs enabled.
64 BET input Field BET (Bit Error Test) entry (low-speed LVCMOS input). 0 = Normal operation; 1 = Field BET operation.
65 EXPGND power_in Exposed pad ground on the bottom of the QFN64 package. Must be tied to the PCB ground plane through an array of thermal/electrical vias.

Key specifications

Parameter Value
Manufacturer THine Elec
Package QFN-64-EP(9x9)
Category Interface
Pins 65

Ordering variants

Same part, different packaging or reel option.

  • THCV236-NNTA

CAD (KiCad official)

  • Symbol: THCV236-NNTA
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: thcv236-nnta-etched.step / thcv236-nnta-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); thcv236-nnta.step / thcv236-nnta.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: THine Elec datasheet (68 pp, sha256 a3b17bdaad942249, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF