component

TF2117-TAH

Public Made by Adom

by adom

TFSS Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icstf2117-tahfactory-2.0.0extractor-text

Verified TF2117-TAH

by Ray · last 5 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

5 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TF2117-TAH · SOIC-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 10-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-qich_106/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tf2117-tah.kicad_sym✓ tf2117-tah.kicad_mod✓ tf2117-tah.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers tf2117-tah: viewers · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
tf2117-tah-etched.glb Publish 0.1.0 · Ray 2d ago
tf2117-tah-etched.step tf2117-tah: factory component page (tier=lcsc) · Ray 2d ago
tf2117-tah-hero.glb tf2117-tah: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
tf2117-tah-hero.overlay.json Publish 0.1.0 · Ray 2d ago
tf2117-tah.glb Publish 0.1.0 · Ray 2d ago
tf2117-tah.kicad_mod Publish 0.1.0 · Ray 2d ago
tf2117-tah.kicad_sym Publish 0.1.0 · Ray 2d ago
tf2117-tah.lbr Publish 0.1.0 · Ray 2d ago
tf2117-tah.step Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier lcsc, 8 pins · Ray 2d ago

TF2117-TAH

TFSS · Gate Drive ICs · SOIC-8

TF2117-TAH from TFSS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Logic and gate drive supply, recommended operating range 10V to 20V (absolute maximum -0.3V to +24V).
2 IN input Logic input for gate driver output HO, in phase with HO (TF2117), Schmitt triggered with internal pull down and referenced to COM.
3 COM power_in Logic ground, the reference for the logic input and output parameters.
4 NC unconnected No connect.
5 NC unconnected No connect.
6 VS power_in High-side floating supply return, recommended offset voltage up to 600V.
7 HO output High-side gate drive output swinging between VS and VB for driving one N-channel MOSFET or IGBT.
8 VB power_in High-side floating supply, recommended VS+10V to VS+20V (absolute maximum -0.3V to +624V).

Key specifications

Parameter Value
Manufacturer TFSS
Package SOIC-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
High side floating supply voltage (VB), absolute maximum VB -0.3 624 V 4
Logic supply voltage (VCC), absolute maximum VCC -0.3 24 V 4
Logic input voltage (VIN), absolute maximum lower bound VIN -0.3 V 4
Allowable offset supply voltage transient dVS/dt 50 V/ns 4
Junction temperature TJ 150 °C 4
Storage temperature TS -55 150 °C 4
Low side and logic fixed supply voltage VCC 10 20 V 4
Logic input voltage (IN/IN*) VIN 0 V 4
High side floating supply offset voltage VS 600 V logic operational (NOTE3) 4
Ambient temperature TA -40 125 °C 4
Logic 1 input voltage VIH 9.5 V NOTE 5 5
Logic 0 input voltage VIL 6 V 5
High level output voltage, VBIAS - VO VOH 0.05 0.2 V IO = 2mA 5
Low level output voltage, VO VOL 0.02 0.1 V IO = 2mA 5
Offset supply leakage current ILK 50 mA VB = VS = 600V 5
Quiescent VBS supply current IBSQ 50 240 mA VIN = 0V or VCC 5
Quiescent VCC supply current ICCQ 70 340 mA VIN = 0V or VCC 5
Logic 1 input bias current IIN+ 20 40 mA VIN = VCC 5
VBS supply under-voltage positive going threshold VBSUV+ 7.6 8.6 9.6 V 5
VBS supply under-voltage negative going threshold VBSUV- 7.2 8.2 9.2 V 5
VCC supply under-voltage positive going threshold VCCUV+ 7.6 8.6 9.6 V 5
VCC supply under-voltage negative going threshold VCCUV- 7.2 8.2 9.2 V 5
Output high short circuit pulsed current IO+ 200 290 mA VO = 0V, VIN = Logic 1, PW ≤ 10 ms 5
Output low short circuit pulsed current IO- 420 600 mA VO = 15V, VIN = Logic 0, PW ≤ 10 ms 5
Turn-on propagation delay tON 125 200 ns VBIAS = 15V, CL = 1000pF, TA = 25 °C; VS = 0V 6
Turn-off propagation delay tOFF 105 180 ns VBIAS = 15V, CL = 1000pF, TA = 25 °C; VS = 600V 6
Turn-on rise time tr 75 130 ns VBIAS = 15V, CL = 1000pF, TA = 25 °C 6
Turn-off fall time tf 35 65 ns VBIAS = 15V, CL = 1000pF, TA = 25 °C 6
SOIC-8 junction-to-ambient thermal resistance RθJA 200 °C/W standard JEDEC 2-layer FR-4 board (NOTE2) 4

CAD (KiCad official)

  • Symbol: TF2117-TAH
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tf2117-tah-etched.step / tf2117-tah-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tf2117-tah.step / tf2117-tah.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TFSS datasheet (10 pp, sha256 4e0118e505edc3d8, retrieved 2026-11-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF