# TF2110M-TEH

**TFSS** · Gate Drivers · SOIC-16-300mil

TF2110M-TEH from TFSS, in a SOIC-16-300mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LO | output | Low-side gate driver output pin, in phase with LIN, swing limited to -0.3V to VCC+0.3V. |
| 2 | COM | power_in | Low-side gate driver power supply return pin. |
| 3 | VCC | power_in | Low-side gate driver power supply pin, recommended 10V to 20V. |
| 4 | NC | unconnected | No connect pin. |
| 5 | NC | unconnected | No connect pin. |
| 6 | VS | power_in | High-side gate driver floating power supply return pin, offset up to 500V (TF2110) or 600V (TF2113) recommended. |
| 7 | VB | power_in | High-side gate driver floating power supply pin, recommended VS+10V to VS+20V. |
| 8 | HO | output | High-side gate driver output pin, in phase with HIN, swing VS to VB. |
| 9 | NC | unconnected | No connect pin. |
| 10 | NC | unconnected | No connect pin. |
| 11 | VDD | power_in | Logic power supply pin, recommended VSS+3V to VSS+20V. |
| 12 | HIN | input | Logic input pin for the high-side gate driver output; HIN and HO are in phase. |
| 13 | SD | input | Logic input shutdown pin. |
| 14 | LIN | input | Logic input pin for the low side gate driver output; LIN and LO are in phase. |
| 15 | VSS | power_in | Logic ground pin. |
| 16 | NC | unconnected | No connect pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TFSS |
| Package | SOIC-16-300mil |
| Category | Motor Driver ICs |
| Pins | 16 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic "1" input voltage | VIH | 9.5 |  |  | V |  | 4 |
| Logic "0" input voltage | VIL |  |  | 6 | V |  | 4 |
| High level output voltage, VBIAS - VO | VOH |  |  | 1.4 | V | IO = 0A | 4 |
| Low level output voltage, VO | VOL |  |  | 0.15 | V | IO = 20mA | 4 |
| Offset supply leakage current | ILK |  |  | 50 | mA | VB = VS = 500V/600V | 4 |
| Quiescent VBS supply current | IBSQ |  | 55 | 230 | mA | VIN = 0V or VDD | 4 |
| Quiescent VCC supply current | ICCQ |  | 56 | 340 | mA | VIN = 0V or VDD | 4 |
| Quiescent VDD supply current | IDDQ |  | 0.6 | 30 | mA | VIN = 0V or VDD | 4 |
| Logic "1" input bias current | IIN+ |  | 20 | 40 | mA | VIN = VDD | 4 |
| Logic "0" input bias current | IIN- |  |  | 5 | mA | VIN = 0V | 4 |
| VBS supply under-voltage positive going threshold | VBSUV+ | 7.5 | 8.6 | 9.7 | V |  | 4 |
| VBS supply under-voltage negative going threshold | VBSUV- | 7 | 8.2 | 9.4 | V |  | 4 |
| VCC supply under-voltage positive going threshold | VCCUV+ | 7.4 | 8.5 | 9.6 | V |  | 4 |
| VCC supply under-voltage negative going threshold | VCCUV- | 7 | 8.2 | 9.4 | V |  | 4 |
| Output high short circuit pulsed current | IO+ | 2 | 2.5 |  | A | VO = 0V, VIN = VDD, PW ≤ 10 ms | 4 |
| Output low short circuit pulsed current | IO- | 2 | 2.5 |  | A | VO = 15V, VIN = 0V, PW ≤ 10 ms | 4 |
| Turn-on propagation delay | tON |  | 105 | 150 | ns | VS = 0V | 5 |
| Turn-off propagation delay | tOFF |  | 94 | 125 | ns | VS = 500V/600V | 5 |
| Shut down propagation delay | tSD |  | 70 | 140 | ns | VS = 500V/600V | 5 |
| Turn-on rise time | tr |  | 15 | 35 | ns | VBIAS = 15V, TA = 25 °C, CL = 1000pF, VSS = COM | 5 |
| Turn-off fall time | tf |  | 13 | 25 | ns | VBIAS = 15V, TA = 25 °C, CL = 1000pF, VSS = COM | 5 |
| Delay Matching (TF2110) | tDM |  |  | 10 | ns | TF2110 | 5 |
| High side floating supply offset voltage (TF2110) | VS |  |  | 500 | V | NOTE 3: logic operational for VS = -4V to +500V; logic state held for VS = -4V to -VBS | 3 |
| Low side fixed supply voltage | VCC | 10 |  | 20 | V |  | 3 |
| Low side output voltage | VLO | 0 |  |  | V |  | 3 |
| Logic supply offset voltage | VSS | -5 |  | 5 | V | NOTE 4: when VDD < 5V, minimum VSS offset is limited to -VDD | 3 |
| Ambient temperature | TA | -40 |  | 125 | °C |  | 3 |
| High side floating supply voltage (TF2110) | VB | -0.3 |  | 524 | V |  | 3 |
| Offset supply voltage transient | dVS/dt |  |  | 50 | V/ns |  | 3 |
| Low side fixed supply voltage | VCC | -0.3 |  | 24 | V |  | 3 |
| Low side output voltage | VLO | -0.3 |  |  | V |  | 3 |
| Logic supply voltage | VDD | -0.3 |  |  | V |  | 3 |
| Junction temperature | TJ |  |  | 150 | °C |  | 3 |
| Storage temperature | TSTG | -55 |  | 150 | °C |  | 3 |

## CAD (KiCad official)

- Symbol: `TF2110M-TEH`
- Footprint: `Package_SO:SOIC-16_3.9x9.9mm_P1.27mm`
- 3D model: SOIC-16-300mil (KiCad packages3D, STEP)
- 3D model files: `tf2110m-teh-etched.step` / `tf2110m-teh-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tf2110m-teh.step` / `tf2110m-teh.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TFSS datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588944835474018304) (14 pp, sha256 `7f2fedc936e0824a`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text+vision), consensus `claude-opus-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tf2110m-teh-datasheet.pdf)