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TF2005M-TAH

Public Made by Adom

by adom

TFSS Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TF2005M-TAH

TFSS · Gate Drivers · SOIC-8

TF2005M-TAH from TFSS, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Low-side and logic fixed supply, recommended 10V to 20V (absolute max 24V).
2 HIN input Logic input for high-side gate driver output (HO), in phase; Schmitt triggered with internal pull-down, VIH 2.5V min, VIL 0.6V max.
3 LIN input Logic input for low-side gate driver output (LO), in phase; Schmitt triggered with internal pull-down, VIH 2.5V min, VIL 0.6V max.
4 COM power_in Low-side return (ground reference for logic inputs and outputs).
5 LO output Low-side gate drive output, swings from 0V to VCC.
6 VS power_in High-side floating supply return, operating offset up to 200V (logic operational for VS = -5V to +200V).
7 HO output High-side gate drive output, swings from VS to VB.
8 VB power_in High-side floating supply, VS+10V to VS+20V recommended (absolute max 224V).

Key specifications

Parameter Value
Manufacturer TFSS
Package SOIC-8
Category Motor Driver ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low side and logic fixed supply voltage VCC 10 20 V 3
High side floating supply offset voltage VS 200 V NOTE3 logic operational for VS = -5 to +200V 3
Low side output voltage VLO 0 V 3
Logic input voltage (HIN and LIN) VIN 0 5 V 3
Ambient temperature TA -40 125 °C 3
VB - High side floating supply voltage VB -0.3 224 V 3
VCC - Low side and logic fixed supply voltage VCC -0.3 24 V 3
Offset supply voltage transient dVS / dt 50 V/ns 3
VLO - Low side output voltage VLO -0.3 V 3
VIN - Logic input voltage (HIN and LIN) VIN -0.3 V 3
TJ - Junction operating temperature TJ 150 °C 3
TL - Lead temperature TL 300 °C soldering, 10s 3
Tstg - Storage temperature range Tstg -55 150 °C 3
Logic "1" input voltage VIH 2.5 V 4
Logic "0" input voltage VIL 0.6 V 4
High level output voltage, VBIAS - VO VOH 0.05 0.2 V IO = 2mA 4
Low level output voltage, VO VOL 0.02 0.1 V IO = 2mA 4
Offset supply leakage current ILK 50 mA VB = VS = 200V 4
Quiescent VBS supply current IBSQ 20 75 130 mA VIN = 0V or 5V 4
Quiescent VCC supply current ICCQ 60 120 180 mA VIN = 0V or 5V 4
Logic "1" input bias current IIN+ 5 20 mA VIN = 5V 4
Logic "0" input bias current IIN- 2 mA VIN = 0V 4
VCC supply under-voltage positive going threshold VCCUV+ 7 8.4 9.8 V 4
VCC supply under-voltage negative going threshold VCCUV- 6.4 7.8 9 V 4
VBS supply under-voltage positive going threshold VBSUV+ 7 8.4 9.8 V 4
VCC supply under-voltage negative going threshold (VBS row as printed) VBSUV- 6.4 7.8 9 V 4
Output high short circuit pulsed current IO+ 130 290 mA VO = 0V, VIN = Logic "1", PW ≤ 10 ms 4
Output low short circuit pulsed current IO- 270 600 mA VO = 15V, VIN = Logic "0", PW ≤ 10 ms 4
Turn-on propagation delay tON 220 300 ns VS = 0V 4
Turn-off propagation delay tOFF 200 280 ns VS = 0V or 200V 4
Turn-on rise time tr 100 220 ns 4
Turn-off fall time tf 35 80 ns VS = 0V 4
Delay matching tDM 30 ns 4
SOIC-8 thermal resistance, junction-to-ambient θJA 200 °C/W NOTE2 3

CAD (KiCad official)

  • Symbol: TF2005M-TAH
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tf2005m-tah-etched.step / tf2005m-tah-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tf2005m-tah.step / tf2005m-tah.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TFSS datasheet (7 pp, sha256 9151681e64b86d65, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF