component
TEA2096T
Public Made by Adomby adom
NXP Semicon Power Management - Specialized, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTEA2096T
NXP Semicon · Power Management - Specialized · SOIC-8
TEA2096T from NXP Semicon, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GDB | output | Gate drive output for SR MOSFET B; the driver output voltage is limited to VG(max) (10.4 to 11.0 V at VCC = 12 V) and is actively pulled low during start-up and UVLO. |
| 2 | GND | power_in | Ground reference for the IC; all voltages in the characteristics are measured with respect to this pin. |
| 3 | DSB | input | Drain sense input for synchronous timing of MOSFET B, capable of handling input voltages up to 200 V (DC range −0.8 V to +200 V). |
| 4 | SSB | input | Source sense input for MOSFET B, to be connected as close as possible to the source pin of the external SR MOSFET; DC limits are −0.4 V to +0.4 V. |
| 5 | SSA | input | Source sense input for MOSFET A, to be connected as close as possible to the source pin of the external SR MOSFET; DC limits are −0.4 V to +0.4 V. |
| 6 | DSA | input | Drain sense input for synchronous timing of MOSFET A, capable of handling input voltages up to 200 V (DC range −0.8 V to +200 V). |
| 7 | VCC | power_in | Supply voltage for the IC, recommended 4.75 V to 38 V (absolute maximum −0.4 V to +38 V), decoupled with an extra capacitor placed as close as possible to the IC between VCC and GND. |
| 8 | GDA | output | Gate drive output for SR MOSFET A; the driver output voltage is limited to VG(max) (10.4 to 11.0 V at VCC = 12 V) and is actively pulled low during start-up and UVLO. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | NXP Semicon |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCC supply voltage (absolute maximum) | VCC | -0.4 | 38 | V | 9 | ||
| Drain sense voltage A | Vsense(D)A | -0.8 | 200 | V | DC | 9 | |
| Drain sense voltage B | Vsense(D)B | -0.8 | 200 | V | DC | 9 | |
| Source sense voltage A | Vsense(S)A | -0.4 | 0.4 | V | DC | 9 | |
| Source sense voltage B | Vsense(S)B | -0.4 | 0.4 | V | DC | 9 | |
| Voltage on pin GDA | VGDA | -0.4 | 12 | V | DC | 9 | |
| Voltage on pin GDB | VGDB | -0.4 | 12 | V | DC | 9 | |
| Maximum frequency | fmax | 1 | MHz | if not limited by Tj | 9 | ||
| Storage temperature | Tstg | -55 | 150 | °C | 9 | ||
| Junction temperature (absolute maximum) | Tj | -40 | 150 | °C | 9 | ||
| ESD human body model | VESD | 2000 | V | HBM | 9 | ||
| ESD charged device model | VESD | 500 | V | CDM | 9 | ||
| VCC supply voltage (recommended operating) | VCC | 4.75 | 38 | V | 9 | ||
| Junction temperature (recommended operating) | Tj | -40 | 125 | °C | 9 | ||
| Start voltage | Vstart | 4.3 | 4.5 | 4.7 | V | 10 | |
| Stop voltage | Vstop | 4 | 4.2 | 4.4 | V | 10 | |
| Operating supply current, energy-save | ICC(oper) | 60 | 80 | 100 | μA | energy-save | 10 |
| Operating supply current, normal operation | ICC(oper) | 0.6 | 0.8 | 1.1 | mA | normal operation (without gate charge) | 10 |
| Energy save mode activation time | tact(es) | 85 | 110 | 135 | μs | 10 | |
| Driver activation voltage | Vact(drv) | -450 | -400 | -350 | mV | Vsense(S)A/Vsense(S)B = 0 V | 10 |
| Driver regulation voltage | Vreg(drv) | -36 | -29 | -23 | mV | Vsense(S)A/Vsense(S)B = 0 V | 10 |
| Switch-off voltage | Vswoff | 60 | 150 | 200 | mV | Vsense(S)A/Vsense(S)B = 0 V | 10 |
| Gate pull-down resistance | Rpd(G) | 2 | 2.5 | 3 | Ω | VDS = 12 V; IG = 100 mA | 10 |
| Maximum gate voltage at VCC = 5 V | VG(max) | 4.98 | 4.99 | 5 | V | VGDA/VGDB at VCC = 5 V | 10 |
| Maximum gate voltage at VCC = 12 V | VG(max) | 10.4 | 10.7 | 11 | V | VGDA/VGDB at VCC = 12 V | 10 |
| Maximum gate voltage at VCC = 38 V | VG(max) | 10.6 | 10.9 | 11.2 | V | VGDA/VGDB at VCC = 38 V | 10 |
| Driver activation delay time | td(act)(drv) | 80 | ns | Vsense(S)A/Vsense(S)B = 0 V; normal operation; time from step on VDSA/VDSB (2 V to −0.5 V) to rising of VGDA/VGDB at 10 % of end value | 10 | ||
| Driver deactivation delay time | td(deact)(drv) | 40 | ns | Vsense(S)A/Vsense(S)B = 0 V; normal operation; time from step on VDSA/VDSB (−0.5 V to 2 V) to falling of VGDA/VGDB at 90 % of begin value | 10 | ||
| Interlock delay time | td | 200 | ns | 10 | |||
| Source current (peak) | Isource | -0.3 | A | peak current at VDS = −0.5 V; VG = 0 V | 10 | ||
| Sink current | Isink | 1 | A | 10 | |||
| Sink current (peak) | Isink | 2 | A | peak current at VDS = 0.25 V; VG = 5 V | 10 | ||
| Thermal resistance junction to ambient | Rth(j-a) | 135 | K/W | SO8 package; PCB 1 layer; 35 μm Cu; 60 mm x 125 mm | 9 | ||
| Thermal resistance junction to case | Rth(j-c) | 50 | K/W | SO8 package | 9 |
CAD (KiCad official)
- Symbol:
TEA2096T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tea2096t-etched.step/tea2096t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tea2096t.step/tea2096t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: NXP Semicon datasheet (18 pp, sha256
d8dffb07c801ff93, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).