component

TEA1708T

Public Made by Adom

by adom

NXP Semicon Battery Management ICs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icstea1708tfactory-2.0.0extractor-text

Verified TEA1708T

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier mfr, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TEA1708T · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 12-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-rlpuhs63/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ tea1708t.kicad_sym✓ tea1708t.kicad_mod✓ tea1708t.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers tea1708t: viewers · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago
tea1708t-etched.glb Publish 0.1.0 · Ray 8d ago
tea1708t-etched.step tea1708t: factory component page (tier=mfr) · Ray 8d ago
tea1708t-hero.glb tea1708t: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
tea1708t-hero.overlay.json Publish 0.1.0 · Ray 8d ago
tea1708t.glb Publish 0.1.0 · Ray 8d ago
tea1708t.kicad_mod Publish 0.1.0 · Ray 8d ago
tea1708t.kicad_sym Publish 0.1.0 · Ray 8d ago
tea1708t.lbr Publish 0.1.0 · Ray 8d ago
tea1708t.step Publish 0.1.0 · Ray 8d ago
verification.json Verified: Published by the parts factory: tier mfr, 8 pins · Ray 8d ago

TEA1708T

NXP Semicon · Battery Management ICs · SO-8

TEA1708T from NXP Semicon, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 n.c. unconnected Not connected.
2 TMR2 passive Timer pin 2; the external low-voltage capacitor between TMR1 and TMR2 sets the discharge delay, with 10 nF to 22 nF recommended for 50 Hz or 60 Hz mains.
3 n.c. unconnected Not connected.
4 TMR1 passive Timer pin 1; the external low-voltage capacitor between TMR1 and TMR2 sets the discharge delay, with values below 10 nF not to be used.
5 HV2 passive High-voltage mains connection 2; the pins HV1 and HV2 are fully symmetrical and the internal clamp activates above 500 V.
6 n.c. unconnected Not connected.
7 n.c. unconnected Not connected.
8 HV1 passive High-voltage mains connection 1; the pins HV1 and HV2 are fully symmetrical and the internal clamp activates above 500 V.

Key specifications

Parameter Value
Manufacturer NXP Semicon
Package SO-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
voltage between pin TMR1 and pin TMR2 VTMR1-TMR2 -0.4 3.5 V 0 μA > Idch(tmr) < 10 μA 5
voltage between pin HV1 and pin HV2 VHV1-HV2 -410 410 V normal operation, so no mains surge 5
current on pin HV IHV -15 15 mA both HV pins; t < 2 ms, during mains surge 5
total power dissipation Ptot 0.5 W Tamb < 75 °C 5
storage temperature Tstg -55 150 °C 5
junction temperature Tj -40 150 °C 5
ESD voltage human body model (HBM) pins HV1 and HV2 VESD 1000 V class 1 5
ESD voltage human body model (HBM) all other pins VESD 4000 V 5
ESD voltage charged device model (CDM) all pins VESD 750 V 5
current on pin HV, current limited IHV 2.5 3.5 4.5 μA both HV pins; VHV1 > 50 V; VHV2 > 50 V; VTMR < 1.2 V 6
current on pin HV, current limited IHV 1.8 2.3 2.8 mA current limited; VTMR > 1.2 V 6
clamp voltage Vclamp 475 500 525 V 6
charge threshold voltage Vth(ch) 19 21 23 V 6
discharge activation threshold voltage Vth(act)dch 1.1 1.2 1.3 V to discharge the X-capacitor 6
timer discharge current Idch(tmr) -1.2 -0.95 -0.7 μA 6
thermal resistance from junction to ambient Rth(j-a) 160 K/W in free air; JEDEC test board 5
thermal resistance from junction to case Rth(j-c) 72 K/W in free air; JEDEC test board 5

CAD (KiCad official)

  • Symbol: TEA1708T
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: tea1708t-etched.step / tea1708t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tea1708t.step / tea1708t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: NXP Semicon datasheet (12 pp, sha256 48f8e35550e9a469, retrieved 2026-10-30, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF