TDES954RGZT

TEXAS INSTRUMENTS · Global Sourcing Parts · VQFN-48(7x7)

TDES954RGZT from TEXAS INSTRUMENTS, in a VQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	I2C_SDA	bidirectional	I2C serial data line for the control bus, open-drain, requiring an external 2 kΩ to 4.7 kΩ pullup to a 1.8 V or 3.3 V rail, with inputs 3.3 V tolerant.
2	I2C_SCL	bidirectional	I2C serial clock line, open-drain, requiring an external 2 kΩ to 4.7 kΩ pullup to a 1.8 V or 3.3 V rail, with inputs 3.3 V tolerant.
3	VDD11_D	power_in	1.1 V internal rail decoupling pin; with VDD_SEL low it must not be connected to a 1.1 V rail and needs 0.1 to 0.01 µF plus 4.7 µF to GND, and with VDD_SEL high it connects to an external 1.1 V supply with 0.01 µF plus 1 µF to GND.
4	XOUT	output	Crystal oscillator output for a 25 MHz parallel 18 pF load crystal, to be left NC when XIN/REFCLK is driven by a reference clock.
5	XIN/REFCLK	input	Reference clock or crystal input, requiring a 23 MHz to 26 MHz clock (100 ppm) or an external crystal between XIN and XOUT, and REFCLK must be continuous.
6	BISTEN	input	BIST enable strap: high enables BIST mode and low disables it, and it should be connected directly to GND if unused.
7	VDDIO	power_in	Supply for the single-ended outputs and control inputs at 1.8 V or 3.3 V, where a 1.8 V supply must be within ±100 mV of VDD18, with a minimum 1 µF and 0.01 µF capacitor to GND per pin.
8	GPIO6	bidirectional	General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused.
9	GPIO5	bidirectional	General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused.
10	GPIO4	bidirectional	General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused.
11	CSI_CLK0N	output	Negative leg of the CSI-2 D-PHY differential clock lane 0 output to the processor, left NC if unused.
12	CSI_CLK0P	output	Positive leg of the CSI-2 D-PHY differential clock lane 0 output to the processor, left NC if unused.
13	CSI_D0N	output	Negative leg of CSI-2 D-PHY differential data lane 0 output to the processor, left NC if unused.
14	CSI_D0P	output	Positive leg of CSI-2 D-PHY differential data lane 0 output to the processor, left NC if unused.
15	CSI_D1N	output	Negative leg of CSI-2 D-PHY differential data lane 1 output to the processor, left NC if unused.
16	CSI_D1P	output	Positive leg of CSI-2 D-PHY differential data lane 1 output to the processor, left NC if unused.
17	VDD18_CSI	power_in	1.8 V (±5%) supply for the CSI-2 output block, requiring 1 µF and 0.01 µF capacitors to GND.
18	CSI_CLK1N	output	Negative leg of the CSI-2 D-PHY differential clock lane 1 output, used for the replicated output in 2-channel replicate mode, left NC if unused.
19	CSI_CLK1P	output	Positive leg of the CSI-2 D-PHY differential clock lane 1 output, used for the replicated output in 2-channel replicate mode, left NC if unused.
20	VDD11_CSI	power_in	1.1 V CSI rail; with VDD_SEL low it must not be connected to a 1.1 V rail and needs 0.1 to 0.01 µF plus 4.7 µF to GND, and with VDD_SEL high it connects to an external 1.1 V supply with 0.01 µF plus 10 µF to GND.
21	CSI_D2N	output	Negative leg of CSI-2 D-PHY differential data lane 2 output to the processor, left NC if unused.
22	CSI_D2P	output	Positive leg of CSI-2 D-PHY differential data lane 2 output to the processor, left NC if unused.
23	CSI_D3N	output	Negative leg of CSI-2 D-PHY differential data lane 3 output to the processor, left NC if unused.
24	CSI_D3P	output	Positive leg of CSI-2 D-PHY differential data lane 3 output to the processor, left NC if unused.
25	GPIO3/INTB	bidirectional	Open-drain active-low GPIO3 that can serve as the INTB interrupt, requiring a 4.7 kΩ pullup to VDDIO, with the function set by status registers.
26	GPIO2	bidirectional	General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused.
27	GPIO1	bidirectional	General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused.
28	GPIO0	bidirectional	General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused.
29	VDDIO	power_in	Supply for the single-ended outputs and control inputs at 1.8 V or 3.3 V, where a 1.8 V supply must be within ±100 mV of VDD18, with a minimum 1 µF and 0.01 µF capacitor to GND per pin.
30	PDB	input	Power-down inverted input with 50 kΩ internal pulldown, where high enables the device and low powers it down with CSI-2 outputs tri-stated, it is 3.3 V tolerant, and it should stay low until supplies reach minimum levels.
31	VDD18_FPD1	power_in	1.8 V (±5%) analog supply for V3Link front end block 1, requiring 10 µF and 0.1 µF capacitors to GND at each VDD pin.
32	RIN1+	bidirectional	Positive V3Link receive input for channel 1 that also carries the bidirectional control back channel, must be AC coupled, and should be left NC with RX_PORT_CTL bit 1 cleared if unused.
33	RIN1-	bidirectional	Negative V3Link receive input for channel 1 that also carries the bidirectional control back channel, must be AC coupled, and should be left NC with RX_PORT_CTL bit 1 cleared if unused.
34	VDD11_FPD1	power_in	1.1 V analog rail for V3Link front end block 1; with VDD_SEL low it must not be connected to a 1.1 V rail, and with VDD_SEL high it connects to an external 1.1 V supply with 0.01 µF to GND and a 10 µF capacitor shared with VDD11_FPD0.
35	IDX	input	I2C device ID address strap sampled after enable, set with a pullup to VDD18 and pulldown to GND as a voltage divider.
36	VDD18_P1	power_in	1.8 V (±5%) digital supply, requiring 0.01 µF capacitors to GND at each VDD pin along with 10 µF bulk decoupling.
37	MODE	input	Mode select strap that sets the V3Link operating mode from a voltage divider on VDD18, sampled 1 ms after PDB goes high.
38	CMLOUTP	output	Positive monitor loop-through differential output, typically routed to test points or left NC and terminated with 100 Ω differential when monitored.
39	CMLOUTN	output	Negative monitor loop-through differential output, typically routed to test points or left NC and terminated with 100 Ω differential when monitored.
40	VDD18_FPD0	power_in	1.8 V (±5%) analog supply for V3Link front end block 0, requiring 10 µF and 0.1 µF capacitors to GND at each VDD pin.
41	RIN0+	bidirectional	Positive V3Link receive input for channel 0 that also carries the bidirectional control back channel, must be AC coupled, and should be left NC with RX_PORT_CTL bit 0 cleared if unused.
42	RIN0-	bidirectional	Negative V3Link receive input for channel 0 that also carries the bidirectional control back channel, must be AC coupled, and should be left NC with RX_PORT_CTL bit 0 cleared if unused.
43	VDD11_FPD0	power_in	1.1 V analog rail for V3Link front end block 0; with VDD_SEL low it must not be connected to a 1.1 V rail, and with VDD_SEL high it connects to an external 1.1 V supply with 0.01 µF to GND and a 10 µF capacitor shared with VDD11_FPD1.
44	RES	input	Reserved pin that must be tied to GND for normal operation.
45	VDD18_P0	power_in	1.8 V (±5%) digital supply, requiring 0.01 µF capacitors to GND at each VDD pin along with 10 µF bulk decoupling.
46	VDD_SEL	input	Strap that selects the 1.1 V supply mode: LOW selects the internal 1.1 V LDO on VDD11, HIGH selects an external 1.1 V supply that must stay below VDD18 and be applied after VDD18.
47	PASS	output	PASS status output that is high when pass conditions are met and low when one or more pass conditions fail, including BIST error-free transmission.
48	LOCK	output	LOCK status output that is high when the V3Link receiver is locked and Rx ports are active, and low when the receiver is unlocked.
49	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	TEXAS INSTRUMENTS
Package	VQFN-48(7x7)
Category	Global Sourcing Parts
Pins	49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Supply voltage VDD18 (VDD18_CSI, VDD18_P1, VDD18_P0, VDD18_FPD0, VDD18_FPD1)	VDD18	-0.3		2.16	V	Over operating free-air temperature range	7
Supply voltage VDD11 (VDD11_CSI, VDD11_D, VDD11_FPD0, VDD11_FPD1)	VDD11	-0.3		1.32	V	Over operating free-air temperature range; and < V(VDD18)	7
VDDIO supply voltage	VDDIO	-0.3		3.96	V	Over operating free-air temperature range	7
V3Link input voltage (RIN0+, RIN0-, RIN1+, RIN1-), device powered up		-0.3		2.75	V	Device powered up (VDD18, VDD11 and VDDIO within recommended operating conditions)	7
V3Link input voltage (RIN0+, RIN0-, RIN1+, RIN1-), device powered down, transient		-0.3		1.45	V	Device powered down (VDD18, VDD11 and VDDIO below recommended operating conditions); transient voltage	7
V3Link input voltage (RIN0+, RIN0-, RIN1+, RIN1-), device powered down, DC		-0.3		1.35	V	Device powered down (VDD18, VDD11 and VDDIO below recommended operating conditions); DC voltage	7
PDB input voltage	PDB	-0.3		3.96	V		7
Open-drain voltage (GPIO3/INTB, I2C_SDA, I2C_SCL)		-0.3		3.96	V		7
Junction temperature				150	°C		7
Storage temperature	Tstg	-65		150	°C		7
Supply voltage V(VDD18)	V(VDD18)	1.71	1.8	1.89	V		8
Supply voltage V(VDD11)	V(VDD11)	1.045	1.1	1.155	V	VDD_SEL = HIGH only	8
Supply voltage offset V(VDD11) - V(VDDIO)		-50		50	mV	V(VDDIO) = 1.8 V	8
LVCMOS supply voltage V(VDDIO)	V(VDDIO)	1.71	1.8	1.89	V	V(VDDIO) = 1.8 V	8
LVCMOS supply voltage V(VDDIO)	V(VDDIO)	3	3.3	3.6	V	V(VDDIO) = 3.3 V	8
Open-drain voltage (GPIO3/INTB, I2C_SDA, I2C_SCL)	V(I2C)	1.71		3.6	V	GPIO3/INTB = V(INTB), I2C_SDA, I2C_SCL = V(I2C)	8
Operating free-air temperature	TA	-20	25	85	°C		8
MIPI data rate (per CSI-2 lane)		368		1664	Mbps		8
MIPI CSI-2 HS clock frequency		184		832	MHz		8
Reference clock oscillator frequency		23		26	MHz	REFCLK or XIN/XOUT	8
Spread-spectrum reference clock modulation percentage, center spread		-0.5		0.5	%	Center spread	8
Spread-spectrum reference clock modulation percentage, down spread		-1		0	%	Down spread	8
Local I2C frequency	fI2C			1	MHz		8
Supply noise V(VDD11)	V(VDD11)			25	mVP-P	DC-50 MHz	8
Supply noise V(VDD18)	V(VDD18)			50	mVP-P	DC-50 MHz	8
Supply noise V(VDDIO) = 1.8 V	V(VDDIO)			50	mVP-P	DC-50 MHz; V(VDDIO) = 1.8 V	8
Supply noise V(VDDIO) = 3.3 V	V(VDDIO)			100	mVP-P	DC-50 MHz; V(VDDIO) = 3.3 V	8
Supply noise on V3Link inputs	RIN0+, RIN1+			10	mVP-P	DC-50 MHz	8
Junction-to-ambient thermal resistance	RθJA		30.2		°C/W	JESD51; RGC (VQFN) 48 pins	8
Junction-to-case (top) thermal resistance	RθJC(TOP)		15.7		°C/W	JESD51; RGC (VQFN) 48 pins	8
Junction-to-case (bottom) thermal resistance	RθJC(BOT)		1.1		°C/W	JESD51; RGC (VQFN) 48 pins	8
Junction-to-board thermal resistance	RθJB		6.7		°C/W	JESD51; RGC (VQFN) 48 pins	8
Total power consumption, MIPI CSI-2 output mode, normal operation	PT		473	564	mW	2 x V3Link input, 4.0 Gbps; CSI-2 1.6 Gbps, 4 data + 1 clock lane; VDD_SEL = LOW, default registers; V(VDD18)=1.89 V, V(VDDIO)=3.6 V	9
Deserializer supply current 2 Rx 4 Tx, VDD18	IDD-R2T4		240	279	mA	2 x V3Link input 4.0 Gbps per Rx port; CSI-2 1.6 Gbps per lane, 4 data + 1 clock; VDD_SEL=LOW, default registers, includes CSI-2 load current; VDD18	9
Deserializer supply current 2 Rx 4 Tx, VDDIO	IDD-R2T4		5	10	mA	2 x V3Link input 4.0 Gbps per Rx port; CSI-2 1.6 Gbps per lane, 4 data + 1 clock; VDD_SEL=LOW; VDDIO	9
Deserializer supply current 2 Rx 4 Tx, VDD18	IDD-R2T4		110	140	mA	2 x V3Link input 4.0 Gbps per Rx port; CSI-2 1.6 Gbps per lane, 4 data + 1 clock; VDD_SEL=HIGH, default registers, includes CSI-2 load current; VDD18	9
Deserializer supply current 2 Rx 4 Tx, VDD11	IDD-R2T4		100	130	mA	2 x V3Link input 4.0 Gbps per Rx port; CSI-2 1.6 Gbps per lane, 4 data + 1 clock; VDD_SEL=HIGH, default registers, includes CSI-2 load current; VDD11	9
Deserializer supply current 1 Rx 4 Tx, VDD18	IDD-R1T4		170	188	mA	1 x V3Link input 4.0 Gbps; CSI-2 800 Mbps per lane, 4 data + 1 clock; VDD_SEL=LOW, default registers, includes CSI-2 load current; VDD18	9
Deserializer supply current 1 Rx 4 Tx, VDD11	IDD-R1T4		80	100	mA	1 x V3Link input 4.0 Gbps; CSI-2 800 Mbps per lane, 4 data + 1 clock; VDD_SEL=HIGH, default registers, includes CSI-2 load current; VDD11	9
Deserializer shutdown current, VDD18	IDDZ		82	115	mA	Power down; PDB = HIGH to LOW, VDD_SEL = LOW; VDD18	10
Deserializer shutdown current, VDD11	IDDZ		30	110	mA	Power down; PDB = HIGH to LOW, VDD_SEL = HIGH; VDD11	10
High level output voltage	VOH	2.4			V	3.3 V LVCMOS; IOH = -4 mA, V(VDDIO) = 3.0 to 3.6 V; GPIO[6:4], GPIO[2:0], LOCK, PASS	11
Low level output voltage	VOL			0.4	V	3.3 V LVCMOS; IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V; GPIO[6:0], LOCK, PASS	11
High level input voltage	VIH	2			V	3.3 V LVCMOS; V(VDDIO) = 3 to 3.6 V; GPIO[6:0], BISTEN	11
High level input voltage	VIH	1.17			V	3.3 V LVCMOS; V(VDDIO) = 3 to 3.6 V; PDB, XIN/REFCLK, VDD_SEL	11
Low level input voltage	VIL			0.8	V	3.3 V LVCMOS; V(VDDIO) = 3 to 3.6 V; GPIO[6:0], BISTEN	11
Low level input voltage	VIL			0.63	V	3.3 V LVCMOS; V(VDDIO) = 3 to 3.6 V; PDB, XIN/REFCLK, VDD_SEL	11
Input high current, internal pulldown enabled	IIH	-190		190	μA	VIN = 3 to 3.6 V, internal pulldown enabled; GPIO[6:0], PDB, BISTEN	11
Input low current	IIL	-20		30	μA	VIN = 0 V; GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN	11
TRI-STATE output current	IOZ	-25		35	μA	VOUT = 0 V or V(VDDIO), PDB = L; GPIO[7:0], LOCK, PASS	11
Output low level, standard-mode/fast-mode	VOL	0		0.4	V	IOL = 3 mA; I2C_SDA, I2C_SCL	11
Input high current, serial control bus	IIH	-10		10	µA	VIN = V(I2C); I2C_SDA, I2C_SCL	11
Single-ended termination resistor (internal)	RT	40	50	60	Ω	Single-ended; RIN0+, RIN1+	12
Differential internal termination resistor	RT	80	100	120	Ω	Differential; RIN0+/RIN0-, RIN1+/RIN1-	12
Back channel output single-ended voltage	VOUT-BC	190	225	260	mV	RL = 50 Ω, coaxial configuration, forward channel disabled; RIN0+, RIN0-, RIN1+, RIN1-	12
HS transmit static common-mode voltage	VCMTX	150	200	250	mV	CSI_D3P/N through CSI_CLK1P/N	12
HS transmit differential voltage	/VOD/	140	200	270	mV	CSI_D3P/N through CSI_CLK1P/N	12
LPTX high level output voltage (data rate ≤ 1.5 Gbps)	VOH	1.1	1.2	1.3	V	Applicable when the supported data rate is ≤ 1.5 Gbps; CSI_D3P/N through CSI_CLK1P/N	12
Deserializer data lock time, AEQ full range	tDDLT	20		300	ms	CSI mode paired with TSER953, coaxial cable, attenuation 21.6 dB @ 2.1 GHz, AEQ full range 0x00 to 0x3F, SFILTER_CFG = 0xA9	13
Data bit rate (HSTXDBR), REFCLK = 25 MHz	HSTXDBR	400	800	1600	Mbps	REFCLK = 25 MHz; CSI_D0P/N through CSI_CLK1P/N	13
Input low current, 3.3 V LVCMOS	IIL	-20		30	μA	VIN = 0 V; GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN	11

CAD (KiCad official)

Symbol: TDES954RGZT
Footprint: Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm
3D model: VQFN-48(7x7) (KiCad packages3D, STEP)
3D model files: tdes954rgzt-etched.step / tdes954rgzt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tdes954rgzt.step / tdes954rgzt.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: TEXAS INSTRUMENTS datasheet (167 pp, sha256 16b4862198dceafd, retrieved 2026-10-28, tier: manufacturer)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# TDES954RGZT

**TEXAS INSTRUMENTS** · Global Sourcing Parts · VQFN-48(7x7)

TDES954RGZT from TEXAS INSTRUMENTS, in a VQFN-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I2C_SDA | bidirectional | I2C serial data line for the control bus, open-drain, requiring an external 2 kΩ to 4.7 kΩ pullup to a 1.8 V or 3.3 V rail, with inputs 3.3 V tolerant. |
| 2 | I2C_SCL | bidirectional | I2C serial clock line, open-drain, requiring an external 2 kΩ to 4.7 kΩ pullup to a 1.8 V or 3.3 V rail, with inputs 3.3 V tolerant. |
| 3 | VDD11_D | power_in | 1.1 V internal rail decoupling pin; with VDD_SEL low it must not be connected to a 1.1 V rail and needs 0.1 to 0.01 µF plus 4.7 µF to GND, and with VDD_SEL high it connects to an external 1.1 V supply with 0.01 µF plus 1 µF to GND. |
| 4 | XOUT | output | Crystal oscillator output for a 25 MHz parallel 18 pF load crystal, to be left NC when XIN/REFCLK is driven by a reference clock. |
| 5 | XIN/REFCLK | input | Reference clock or crystal input, requiring a 23 MHz to 26 MHz clock (100 ppm) or an external crystal between XIN and XOUT, and REFCLK must be continuous. |
| 6 | BISTEN | input | BIST enable strap: high enables BIST mode and low disables it, and it should be connected directly to GND if unused. |
| 7 | VDDIO | power_in | Supply for the single-ended outputs and control inputs at 1.8 V or 3.3 V, where a 1.8 V supply must be within ±100 mV of VDD18, with a minimum 1 µF and 0.01 µF capacitor to GND per pin. |
| 8 | GPIO6 | bidirectional | General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused. |
| 9 | GPIO5 | bidirectional | General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused. |
| 10 | GPIO4 | bidirectional | General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused. |
| 11 | CSI_CLK0N | output | Negative leg of the CSI-2 D-PHY differential clock lane 0 output to the processor, left NC if unused. |
| 12 | CSI_CLK0P | output | Positive leg of the CSI-2 D-PHY differential clock lane 0 output to the processor, left NC if unused. |
| 13 | CSI_D0N | output | Negative leg of CSI-2 D-PHY differential data lane 0 output to the processor, left NC if unused. |
| 14 | CSI_D0P | output | Positive leg of CSI-2 D-PHY differential data lane 0 output to the processor, left NC if unused. |
| 15 | CSI_D1N | output | Negative leg of CSI-2 D-PHY differential data lane 1 output to the processor, left NC if unused. |
| 16 | CSI_D1P | output | Positive leg of CSI-2 D-PHY differential data lane 1 output to the processor, left NC if unused. |
| 17 | VDD18_CSI | power_in | 1.8 V (±5%) supply for the CSI-2 output block, requiring 1 µF and 0.01 µF capacitors to GND. |
| 18 | CSI_CLK1N | output | Negative leg of the CSI-2 D-PHY differential clock lane 1 output, used for the replicated output in 2-channel replicate mode, left NC if unused. |
| 19 | CSI_CLK1P | output | Positive leg of the CSI-2 D-PHY differential clock lane 1 output, used for the replicated output in 2-channel replicate mode, left NC if unused. |
| 20 | VDD11_CSI | power_in | 1.1 V CSI rail; with VDD_SEL low it must not be connected to a 1.1 V rail and needs 0.1 to 0.01 µF plus 4.7 µF to GND, and with VDD_SEL high it connects to an external 1.1 V supply with 0.01 µF plus 10 µF to GND. |
| 21 | CSI_D2N | output | Negative leg of CSI-2 D-PHY differential data lane 2 output to the processor, left NC if unused. |
| 22 | CSI_D2P | output | Positive leg of CSI-2 D-PHY differential data lane 2 output to the processor, left NC if unused. |
| 23 | CSI_D3N | output | Negative leg of CSI-2 D-PHY differential data lane 3 output to the processor, left NC if unused. |
| 24 | CSI_D3P | output | Positive leg of CSI-2 D-PHY differential data lane 3 output to the processor, left NC if unused. |
| 25 | GPIO3/INTB | bidirectional | Open-drain active-low GPIO3 that can serve as the INTB interrupt, requiring a 4.7 kΩ pullup to VDDIO, with the function set by status registers. |
| 26 | GPIO2 | bidirectional | General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused. |
| 27 | GPIO1 | bidirectional | General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused. |
| 28 | GPIO0 | bidirectional | General-purpose I/O for sensor sync and control, disabled at power-up with a 35 kΩ typical pulldown, and may be left open if unused. |
| 29 | VDDIO | power_in | Supply for the single-ended outputs and control inputs at 1.8 V or 3.3 V, where a 1.8 V supply must be within ±100 mV of VDD18, with a minimum 1 µF and 0.01 µF capacitor to GND per pin. |
| 30 | PDB | input | Power-down inverted input with 50 kΩ internal pulldown, where high enables the device and low powers it down with CSI-2 outputs tri-stated, it is 3.3 V tolerant, and it should stay low until supplies reach minimum levels. |
| 31 | VDD18_FPD1 | power_in | 1.8 V (±5%) analog supply for V3Link front end block 1, requiring 10 µF and 0.1 µF capacitors to GND at each VDD pin. |
| 32 | RIN1+ | bidirectional | Positive V3Link receive input for channel 1 that also carries the bidirectional control back channel, must be AC coupled, and should be left NC with RX_PORT_CTL bit 1 cleared if unused. |
| 33 | RIN1- | bidirectional | Negative V3Link receive input for channel 1 that also carries the bidirectional control back channel, must be AC coupled, and should be left NC with RX_PORT_CTL bit 1 cleared if unused. |
| 34 | VDD11_FPD1 | power_in | 1.1 V analog rail for V3Link front end block 1; with VDD_SEL low it must not be connected to a 1.1 V rail, and with VDD_SEL high it connects to an external 1.1 V supply with 0.01 µF to GND and a 10 µF capacitor shared with VDD11_FPD0. |
| 35 | IDX | input | I2C device ID address strap sampled after enable, set with a pullup to VDD18 and pulldown to GND as a voltage divider. |
| 36 | VDD18_P1 | power_in | 1.8 V (±5%) digital supply, requiring 0.01 µF capacitors to GND at each VDD pin along with 10 µF bulk decoupling. |
| 37 | MODE | input | Mode select strap that sets the V3Link operating mode from a voltage divider on VDD18, sampled 1 ms after PDB goes high. |
| 38 | CMLOUTP | output | Positive monitor loop-through differential output, typically routed to test points or left NC and terminated with 100 Ω differential when monitored. |
| 39 | CMLOUTN | output | Negative monitor loop-through differential output, typically routed to test points or left NC and terminated with 100 Ω differential when monitored. |
| 40 | VDD18_FPD0 | power_in | 1.8 V (±5%) analog supply for V3Link front end block 0, requiring 10 µF and 0.1 µF capacitors to GND at each VDD pin. |
| 41 | RIN0+ | bidirectional | Positive V3Link receive input for channel 0 that also carries the bidirectional control back channel, must be AC coupled, and should be left NC with RX_PORT_CTL bit 0 cleared if unused. |
| 42 | RIN0- | bidirectional | Negative V3Link receive input for channel 0 that also carries the bidirectional control back channel, must be AC coupled, and should be left NC with RX_PORT_CTL bit 0 cleared if unused. |
| 43 | VDD11_FPD0 | power_in | 1.1 V analog rail for V3Link front end block 0; with VDD_SEL low it must not be connected to a 1.1 V rail, and with VDD_SEL high it connects to an external 1.1 V supply with 0.01 µF to GND and a 10 µF capacitor shared with VDD11_FPD1. |
| 44 | RES | input | Reserved pin that must be tied to GND for normal operation. |
| 45 | VDD18_P0 | power_in | 1.8 V (±5%) digital supply, requiring 0.01 µF capacitors to GND at each VDD pin along with 10 µF bulk decoupling. |
| 46 | VDD_SEL | input | Strap that selects the 1.1 V supply mode: LOW selects the internal 1.1 V LDO on VDD11, HIGH selects an external 1.1 V supply that must stay below VDD18 and be applied after VDD18. |
| 47 | PASS | output | PASS status output that is high when pass conditions are met and low when one or more pass conditions fail, including BIST error-free transmission. |
| 48 | LOCK | output | LOCK status output that is high when the V3Link receiver is locked and Rx ports are active, and low when the receiver is unlocked. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | TEXAS INSTRUMENTS |
| Package | VQFN-48(7x7) |
| Category | Global Sourcing Parts |
| Pins | 49 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VDD18 (VDD18_CSI, VDD18_P1, VDD18_P0, VDD18_FPD0, VDD18_FPD1) | VDD18 | -0.3 |  | 2.16 | V | Over operating free-air temperature range | 7 |
| Supply voltage VDD11 (VDD11_CSI, VDD11_D, VDD11_FPD0, VDD11_FPD1) | VDD11 | -0.3 |  | 1.32 | V | Over operating free-air temperature range; and < V(VDD18) | 7 |
| VDDIO supply voltage | VDDIO | -0.3 |  | 3.96 | V | Over operating free-air temperature range | 7 |
| V3Link input voltage (RIN0+, RIN0-, RIN1+, RIN1-), device powered up |  | -0.3 |  | 2.75 | V | Device powered up (VDD18, VDD11 and VDDIO within recommended operating conditions) | 7 |
| V3Link input voltage (RIN0+, RIN0-, RIN1+, RIN1-), device powered down, transient |  | -0.3 |  | 1.45 | V | Device powered down (VDD18, VDD11 and VDDIO below recommended operating conditions); transient voltage | 7 |
| V3Link input voltage (RIN0+, RIN0-, RIN1+, RIN1-), device powered down, DC |  | -0.3 |  | 1.35 | V | Device powered down (VDD18, VDD11 and VDDIO below recommended operating conditions); DC voltage | 7 |
| PDB input voltage | PDB | -0.3 |  | 3.96 | V |  | 7 |
| Open-drain voltage (GPIO3/INTB, I2C_SDA, I2C_SCL) |  | -0.3 |  | 3.96 | V |  | 7 |
| Junction temperature |  |  |  | 150 | °C |  | 7 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 7 |
| Supply voltage V(VDD18) | V(VDD18) | 1.71 | 1.8 | 1.89 | V |  | 8 |
| Supply voltage V(VDD11) | V(VDD11) | 1.045 | 1.1 | 1.155 | V | VDD_SEL = HIGH only | 8 |
| Supply voltage offset V(VDD11) - V(VDDIO) |  | -50 |  | 50 | mV | V(VDDIO) = 1.8 V | 8 |
| LVCMOS supply voltage V(VDDIO) | V(VDDIO) | 1.71 | 1.8 | 1.89 | V | V(VDDIO) = 1.8 V | 8 |
| LVCMOS supply voltage V(VDDIO) | V(VDDIO) | 3 | 3.3 | 3.6 | V | V(VDDIO) = 3.3 V | 8 |
| Open-drain voltage (GPIO3/INTB, I2C_SDA, I2C_SCL) | V(I2C) | 1.71 |  | 3.6 | V | GPIO3/INTB = V(INTB), I2C_SDA, I2C_SCL = V(I2C) | 8 |
| Operating free-air temperature | TA | -20 | 25 | 85 | °C |  | 8 |
| MIPI data rate (per CSI-2 lane) |  | 368 |  | 1664 | Mbps |  | 8 |
| MIPI CSI-2 HS clock frequency |  | 184 |  | 832 | MHz |  | 8 |
| Reference clock oscillator frequency |  | 23 |  | 26 | MHz | REFCLK or XIN/XOUT | 8 |
| Spread-spectrum reference clock modulation percentage, center spread |  | -0.5 |  | 0.5 | % | Center spread | 8 |
| Spread-spectrum reference clock modulation percentage, down spread |  | -1 |  | 0 | % | Down spread | 8 |
| Local I2C frequency | fI2C |  |  | 1 | MHz |  | 8 |
| Supply noise V(VDD11) | V(VDD11) |  |  | 25 | mVP-P | DC-50 MHz | 8 |
| Supply noise V(VDD18) | V(VDD18) |  |  | 50 | mVP-P | DC-50 MHz | 8 |
| Supply noise V(VDDIO) = 1.8 V | V(VDDIO) |  |  | 50 | mVP-P | DC-50 MHz; V(VDDIO) = 1.8 V | 8 |
| Supply noise V(VDDIO) = 3.3 V | V(VDDIO) |  |  | 100 | mVP-P | DC-50 MHz; V(VDDIO) = 3.3 V | 8 |
| Supply noise on V3Link inputs | RIN0+, RIN1+ |  |  | 10 | mVP-P | DC-50 MHz | 8 |
| Junction-to-ambient thermal resistance | RθJA |  | 30.2 |  | °C/W | JESD51; RGC (VQFN) 48 pins | 8 |
| Junction-to-case (top) thermal resistance | RθJC(TOP) |  | 15.7 |  | °C/W | JESD51; RGC (VQFN) 48 pins | 8 |
| Junction-to-case (bottom) thermal resistance | RθJC(BOT) |  | 1.1 |  | °C/W | JESD51; RGC (VQFN) 48 pins | 8 |
| Junction-to-board thermal resistance | RθJB |  | 6.7 |  | °C/W | JESD51; RGC (VQFN) 48 pins | 8 |
| Total power consumption, MIPI CSI-2 output mode, normal operation | PT |  | 473 | 564 | mW | 2 x V3Link input, 4.0 Gbps; CSI-2 1.6 Gbps, 4 data + 1 clock lane; VDD_SEL = LOW, default registers; V(VDD18)=1.89 V, V(VDDIO)=3.6 V | 9 |
| Deserializer supply current 2 Rx 4 Tx, VDD18 | IDD-R2T4 |  | 240 | 279 | mA | 2 x V3Link input 4.0 Gbps per Rx port; CSI-2 1.6 Gbps per lane, 4 data + 1 clock; VDD_SEL=LOW, default registers, includes CSI-2 load current; VDD18 | 9 |
| Deserializer supply current 2 Rx 4 Tx, VDDIO | IDD-R2T4 |  | 5 | 10 | mA | 2 x V3Link input 4.0 Gbps per Rx port; CSI-2 1.6 Gbps per lane, 4 data + 1 clock; VDD_SEL=LOW; VDDIO | 9 |
| Deserializer supply current 2 Rx 4 Tx, VDD18 | IDD-R2T4 |  | 110 | 140 | mA | 2 x V3Link input 4.0 Gbps per Rx port; CSI-2 1.6 Gbps per lane, 4 data + 1 clock; VDD_SEL=HIGH, default registers, includes CSI-2 load current; VDD18 | 9 |
| Deserializer supply current 2 Rx 4 Tx, VDD11 | IDD-R2T4 |  | 100 | 130 | mA | 2 x V3Link input 4.0 Gbps per Rx port; CSI-2 1.6 Gbps per lane, 4 data + 1 clock; VDD_SEL=HIGH, default registers, includes CSI-2 load current; VDD11 | 9 |
| Deserializer supply current 1 Rx 4 Tx, VDD18 | IDD-R1T4 |  | 170 | 188 | mA | 1 x V3Link input 4.0 Gbps; CSI-2 800 Mbps per lane, 4 data + 1 clock; VDD_SEL=LOW, default registers, includes CSI-2 load current; VDD18 | 9 |
| Deserializer supply current 1 Rx 4 Tx, VDD11 | IDD-R1T4 |  | 80 | 100 | mA | 1 x V3Link input 4.0 Gbps; CSI-2 800 Mbps per lane, 4 data + 1 clock; VDD_SEL=HIGH, default registers, includes CSI-2 load current; VDD11 | 9 |
| Deserializer shutdown current, VDD18 | IDDZ |  | 82 | 115 | mA | Power down; PDB = HIGH to LOW, VDD_SEL = LOW; VDD18 | 10 |
| Deserializer shutdown current, VDD11 | IDDZ |  | 30 | 110 | mA | Power down; PDB = HIGH to LOW, VDD_SEL = HIGH; VDD11 | 10 |
| High level output voltage | VOH | 2.4 |  |  | V | 3.3 V LVCMOS; IOH = -4 mA, V(VDDIO) = 3.0 to 3.6 V; GPIO[6:4], GPIO[2:0], LOCK, PASS | 11 |
| Low level output voltage | VOL |  |  | 0.4 | V | 3.3 V LVCMOS; IOL = 4 mA, V(VDDIO) = 3.0 to 3.6 V; GPIO[6:0], LOCK, PASS | 11 |
| High level input voltage | VIH | 2 |  |  | V | 3.3 V LVCMOS; V(VDDIO) = 3 to 3.6 V; GPIO[6:0], BISTEN | 11 |
| High level input voltage | VIH | 1.17 |  |  | V | 3.3 V LVCMOS; V(VDDIO) = 3 to 3.6 V; PDB, XIN/REFCLK, VDD_SEL | 11 |
| Low level input voltage | VIL |  |  | 0.8 | V | 3.3 V LVCMOS; V(VDDIO) = 3 to 3.6 V; GPIO[6:0], BISTEN | 11 |
| Low level input voltage | VIL |  |  | 0.63 | V | 3.3 V LVCMOS; V(VDDIO) = 3 to 3.6 V; PDB, XIN/REFCLK, VDD_SEL | 11 |
| Input high current, internal pulldown enabled | IIH | -190 |  | 190 | μA | VIN = 3 to 3.6 V, internal pulldown enabled; GPIO[6:0], PDB, BISTEN | 11 |
| Input low current | IIL | -20 |  | 30 | μA | VIN = 0 V; GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN | 11 |
| TRI-STATE output current | IOZ | -25 |  | 35 | μA | VOUT = 0 V or V(VDDIO), PDB = L; GPIO[7:0], LOCK, PASS | 11 |
| Output low level, standard-mode/fast-mode | VOL | 0 |  | 0.4 | V | IOL = 3 mA; I2C_SDA, I2C_SCL | 11 |
| Input high current, serial control bus | IIH | -10 |  | 10 | µA | VIN = V(I2C); I2C_SDA, I2C_SCL | 11 |
| Single-ended termination resistor (internal) | RT | 40 | 50 | 60 | Ω | Single-ended; RIN0+, RIN1+ | 12 |
| Differential internal termination resistor | RT | 80 | 100 | 120 | Ω | Differential; RIN0+/RIN0-, RIN1+/RIN1- | 12 |
| Back channel output single-ended voltage | VOUT-BC | 190 | 225 | 260 | mV | RL = 50 Ω, coaxial configuration, forward channel disabled; RIN0+, RIN0-, RIN1+, RIN1- | 12 |
| HS transmit static common-mode voltage | VCMTX | 150 | 200 | 250 | mV | CSI_D3P/N through CSI_CLK1P/N | 12 |
| HS transmit differential voltage | /VOD/ | 140 | 200 | 270 | mV | CSI_D3P/N through CSI_CLK1P/N | 12 |
| LPTX high level output voltage (data rate ≤ 1.5 Gbps) | VOH | 1.1 | 1.2 | 1.3 | V | Applicable when the supported data rate is ≤ 1.5 Gbps; CSI_D3P/N through CSI_CLK1P/N | 12 |
| Deserializer data lock time, AEQ full range | tDDLT | 20 |  | 300 | ms | CSI mode paired with TSER953, coaxial cable, attenuation 21.6 dB @ 2.1 GHz, AEQ full range 0x00 to 0x3F, SFILTER_CFG = 0xA9 | 13 |
| Data bit rate (HSTXDBR), REFCLK = 25 MHz | HSTXDBR | 400 | 800 | 1600 | Mbps | REFCLK = 25 MHz; CSI_D0P/N through CSI_CLK1P/N | 13 |
| Input low current, 3.3 V LVCMOS | IIL | -20 |  | 30 | μA | VIN = 0 V; GPIO[6:0], PDB, XIN/REFCLK, VDD_SEL, BISTEN | 11 |

## CAD (KiCad official)

- Symbol: `TDES954RGZT`
- Footprint: `Package_DFN_QFN:QFN-48-1EP_7x7mm_P0.5mm_EP5.15x5.15mm`
- 3D model: VQFN-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `tdes954rgzt-etched.step` / `tdes954rgzt-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tdes954rgzt.step` / `tdes954rgzt.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [TEXAS INSTRUMENTS datasheet](https://www.ti.com/cn/lit/gpn/tdes954) (167 pp, sha256 `16b4862198dceafd`, retrieved 2026-10-28, tier: manufacturer)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tdes954rgzt-datasheet.pdf)