component
TDC7200PWR
Public Made by Adomby adom
Texas Instruments ADCs/DACs - Special Purpose, TSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTDC7200PWR
Texas Instruments · ADCs/DACs - Special Purpose · TSSOP-14
TDC7200PWR from Texas Instruments, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ENABLE | input | Enable signal to TDC input, active high, provides reset to all digital circuits with 1-100 ns rise/fall time |
| 2 | TRIGG | output | Trigger output signal, rising or falling edge selectable via TRIGG_EDGE bit in CONFIG1 register |
| 3 | START | input | START signal input for time-of-flight measurement, rising or falling edge selectable, 10 ns minimum pulse width |
| 4 | STOP | input | STOP signal input for time-of-flight measurement, rising or falling edge selectable, 10 ns minimum pulse width, supports up to 5 consecutive stops |
| 5 | CLOCK | input | Clock input for TDC calibration and time base, frequency 1 to 16 MHz required for accurate picosecond resolution operation |
| 6 | N.C. | unconnected | Not Connected |
| 7 | GND | power_in | Ground, supply voltage reference for TDC7200 device |
| 8 | INTB | output | Interrupt output to MCU, active low open drain output, VOL 0.35-0.99 V typical, signals measurement completion |
| 9 | DOUT | output | SPI Data Output, high impedance when inactive, VOH 2.31-2.95 V typical, VOL 0.35-0.99 V typical |
| 10 | DIN | input | SPI Data Input for TDC configuration and register access, setup time 4 ns, hold time 4 ns |
| 11 | CSB | input | SPI Chip Select active low, enables SPI communication when low, 40 ns minimum CSB high time between transactions |
| 12 | SCLK | input | SPI clock input, maximum frequency 20 MHz, can idle high or low, 50 ns minimum period at fSCLK = 20 MHz |
| 13 | VREG | power_out | LDO Output terminal for external decoupling capacitor, capacitance 0.4-2.7 µF ceramic, ESR maximum 100 mΩ |
| 14 | VDD | power_in | Power Supply input voltage 2-3.6 V, requires 100 nF ceramic bypass capacitor close to pin |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-14 |
| Category | Data Acquisition |
| Pins | 14 |
CAD (KiCad official)
- Symbol:
TDC7200PWR - Footprint:
Package_SO:TSSOP-14_4.4x5mm_P0.65mm - 3D model: TSSOP-14 (KiCad packages3D, STEP)
- 3D model files:
tdc7200pwr-etched.step/tdc7200pwr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tdc7200pwr.step/tdc7200pwr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (52 pp, sha256
0a0accdd4231b23e, retrieved 2026-09-24, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).