# TD5830C

**Techcode Semicon** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · ESOP-8

TD5830C from Techcode Semicon, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PGOOD | output | Open-drain output that asserts high once VO reaches 92% of its rating voltage. |
| 2 | EN | input | Enable input (active high): a logic low shuts down the output, and the logic-high threshold is 1.2 V minimum with logic-low at 0.2 V maximum. |
| 3 | VIN | power_in | Input voltage (1.2 V to 5.5 V recommended); large bulk capacitance should be placed close to this pin, with a 10 µF ceramic capacitor recommended. |
| 4 | VDD | power_in | Input voltage for the control circuit, 3.0 V to 5.5 V per the recommended operating conditions; VDD must be greater than VOUT + 1.7 V. |
| 5 | NC | unconnected | Not connected. |
| 6 | VOUT | power_out | Power output of the device; a pull-low resistance (typically 150 Ω) exists when the device is disabled via VEN. |
| 7 | ADJ | input | Sets the output voltage through external feedback resistors, with Vo = 0.8 × (R1+R2)/R2 V; R2 (ADJ to GND) should be 1 kΩ to 24 kΩ. |
| 8 | GND | power_in | Reference ground. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Techcode Semicon |
| Package | ESOP-8 |
| Category | Power Management (PMIC) |
| Pins | 9 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| POR Threshold |  | 2.4 | 2.7 | 3 | V |  | 4 |
| POR Hysteresis |  | 0.15 | 0.2 |  | V |  | 4 |
| Adjustable Pin Threshold | VTH_ADJ |  | 0.2 | 0.4 | V | IOUT=1mA | 4 |
| Reference Voltage | VADJ | 0.784 | 0.8 | 0.816 | V | FB=Vout IOUT=1mA TJ=25 ºC | 4 |
| Fixed Output Voltage Range | ΔVOUT | -2 | 0 | 2 | % |  | 4 |
| Line Regulation (VIN) | ΔVLINE_IN |  | 0.2 | 0.6 | % | VIN=VOUT+0.5V TO 5V IOUT=1mA | 4 |
| Load Regulation | ΔVLOAD |  | 0.1 | 1 | % | VIN=VOUT+1V IOUT=1mA TO 3A | 4 |
| Dropout Voltage | VDROP |  | 210 | 350 | mV | IOUT= 3A | 4 |
| Quiescent Current | IQ |  | 0.6 | 1.2 | mA | VDD=5.5V | 4 |
| Current Limit | ILIM | 3.2 | 4.5 |  | A |  | 4 |
| Short Circuit Current |  | 0.5 | 1.8 |  | A | VOUT<0.2V | 4 |
| VDD Shutdown Current | ISHDN |  |  | 1 | uA |  | 4 |
| EN Threshold Logic-Low Voltage | VENL |  |  | 0.2 | V |  | 4 |
| EN Logic-High Voltage | VENH | 1.2 |  |  | V |  | 4 |
| PGOOD Rising Threshold |  |  | 90 | 93 | % |  | 5 |
| PGOOD Hysteresis |  | 3 | 10 |  | % |  | 5 |
| PGOOD Sink Capability |  |  | 0.2 | 0.4 | V | IPGOOD=10mA | 5 |
| PGOOD Delay |  | 0.5 | 1.5 | 5 | mS |  | 5 |
| VDD Input Voltage | VDD | 3 |  | 5.5 | V |  | 4 |
| VIN Supply Voltage | VIN | 1.2 |  | 5.5 | V |  | 4 |
| VOUT Output Voltage | VOUT | 0.8 |  |  | V | when VCNTL-VOUT>1.7V; maximum printed as VIN, VDROP | 4 |
| VOUT Output Current | IOUT | 0 |  | 3 | A |  | 4 |
| ADJ to GND Resistor | R2 | 1 |  | 24 | kΩ |  | 4 |
| VOUT Output Capacitance | COUT | 8 |  | 770 | uF | IOUT = 3A at 25% nominal VOUT | 4 |
| VOUT Output Capacitance | COUT | 8 |  | 1400 | uF | IOUT = 1.5A at 25% nominal VOUT | 4 |
| VOUT Output Capacitance | COUT | 8 |  | 1700 | uF | IOUT = 0.5A at 25% nominal VOUT | 4 |
| ESR of VOUT Output Capacitor | ESRCOUT | 0 |  | 200 | mΩ |  | 4 |
| Ambient Temperature | TA | -40 |  | 85 | ℃ |  | 4 |
| Junction Temperature | TJ | -40 |  | 125 | ℃ |  | 4 |
| VCNTL Supply Voltage (VCNTL to GND) | VCNTL | -0.3 |  | 6 | V |  | 3 |
| VIN Supply Voltage (VIN to GND) | VIN | -0.3 |  | 6 | V |  | 3 |
| VOUT to GND Voltage | VOUT | -0.3 |  |  | V | maximum printed as VIN+0.3 | 3 |
| POK to GND Voltage | POK | -0.3 |  | 7 | V |  | 3 |
| EN, FB to GND Voltage | EN, FB | -0.3 |  |  | V | maximum printed as VCNTL+0.3 | 3 |
| Maximum Junction Temperature | TJ |  |  | 150 | ℃ |  | 3 |
| Storage Temperature Range | TJ | -65 |  | 150 | ℃ | printed as -65°C≤TJ ≤ +150 ℃ | 3 |
| Storage Temperature |  | -65 |  | 150 | ℃ |  | 3 |
| Reflow Temperature (soldering, 10sec) |  |  |  | 260 | ℃ | soldering, 10 sec | 3 |
| Lead Temperature (Soldering, 10 sec) |  |  |  | 260 | ℃ | soldering, 10 sec | 3 |
| ESD Rating (Human Body Model) |  |  |  | 2000 | V | Human Body Model | 3 |
| Operating Temperature Range |  | -40 |  | 125 | ℃ |  | 3 |
| Thermal Resistance Junction to Ambient | θJA |  | 50 |  | ℃/W |  | 3 |
| Thermal Resistance Junction to Case | θJC |  | 20 |  | ℃/W |  | 3 |

## CAD (KiCad official)

- Symbol: `TD5830C`
- Footprint: `Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm`
- 3D model: ESOP-8 (KiCad packages3D, STEP)
- 3D model files: `td5830c-etched.step` / `td5830c-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `td5830c.step` / `td5830c.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Techcode Semicon datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8602996913465802752) (16 pp, sha256 `65451ff3007e25f9`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/td5830c-datasheet.pdf)