component

TD1730

Public Made by Adom

by adom

Techcode Semicon AC-DC Controllers & Regulators, TDFN-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icstd1730factory-2.0.0extractor-text

Verified TD1730

by Ray · last 7 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

7 Nov 2026RayPublished by the parts factory: tier lcsc, 11 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: TD1730 · TDFN-10-EP(3x3) · 11 pins
  • ✓copper: 11 copper pads, none touching another net
  • ✓datasheet: all 11 pin names found in the 17-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-k8h3zwap/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 11 pins = 11 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 11 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ td1730.kicad_sym✓ td1730.kicad_mod✓ td1730.step
Spot something wrong? Report it as an issue Propose a fix Records are signed by members of adom.
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 9h ago
viewers td1730: viewers · Ray 9h ago
package.json Publish 0.1.0 · Ray 9h ago
page.json Set visibility: public · Ray 9h ago
README.md Publish 0.1.0 · Ray 9h ago
td1730-etched.glb Publish 0.1.0 · Ray 9h ago
td1730-etched.step td1730: factory component page (tier=lcsc) · Ray 9h ago
td1730-hero.glb td1730: hero GLB from the etched model (keeps the MPN mark) · Ray 9h ago
td1730-hero.overlay.json Publish 0.1.0 · Ray 9h ago
td1730.glb Publish 0.1.0 · Ray 9h ago
td1730.kicad_mod Publish 0.1.0 · Ray 9h ago
td1730.kicad_sym Publish 0.1.0 · Ray 9h ago
td1730.lbr Publish 0.1.0 · Ray 9h ago
td1730.step Publish 0.1.0 · Ray 9h ago
verification.json Verified: Published by the parts factory: tier lcsc, 11 pins · Ray 9h ago

TD1730

Techcode Semicon · AC-DC Controllers & Regulators · TDFN-10-EP(3x3)

TD1730 from Techcode Semicon, in a TDFN-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 POK output Open-drain power-good output indicating output voltage status, to be connected to +5V through a pull-high resistor.
2 OCSET passive Current-limit threshold setting pin that sources 10 uA through a resistor to GND to monitor the low-side MOSFET drain-source voltage drop.
3 EN input Enable input of the PWM controller, enabled above 1.8V and in shutdown below 0.5V with only low leakage current taken from VCC and VIN.
4 FB input Output voltage feedback pin connected to the resistive divider that sets the output voltage, also monitored by the POK, UVP and OVP circuits.
5 RF input Switching frequency setting pin using resistor RRF (Table 1), where pulling to GND selects automatic PFM/PWM mode and pulling high to POK selects forced PWM mode.
6 LGATE output Low-side MOSFET driver output connected to the low-side MOSFET gate, swinging from GND to VCC.
7 VCC power_in Control circuitry supply input of +5V (4.5V to 5.5V recommended), decoupled with at least 1uF MLCC to GND.
8 PHASE bidirectional Junction of the high-side MOSFET source, output inductor and low-side MOSFET drain, serving as the lower supply rail for the UGATE driver.
9 UGATE output High-side MOSFET driver output connected to the gate of the high-side MOSFET.
10 BOOT power_in Supply input for the UGATE driver and internal level shifter, connected to an external bootstrap capacitor to drive a logic-level N-channel MOSFET.
11 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Techcode Semicon
Package TDFN-10-EP(3x3)
Category Power Management ICs
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output Voltage VOUT 0.7 5.5 V Adjustable output range 5
Regulation Accuracy -0.5 0.5 % TA = 25°C 5
Regulation Accuracy -0.8 0.8 % TA = 0°C ~ 85°C 5
Regulation Accuracy -1 1 % TA = -40°C ~ 85°C 5
FB Input Bias Current IFB 0.02 0.1 uA FB = 0.7V 5
VCC Input Bias Current IVCC 250 520 uA VCC Current, PWM, EN = 5V, VFB = 0.735V, PHASE = 0 5V 5
VCC Shutdown Current IVCC SHDN 0 1 uA EN = GND, VCC = 5V 5
Switching Frequency FSW 115 135 155 kHz RRF = 470k, TA = 25°C, VIN=8V, VOUT=1.1V, IOUT=10A 5
Switching Frequency FSW 140 165 180 kHz RRF = 200k, TA = 25°C, VIN=8V, VOUT=1.1V, IOUT=10A 5
Switching Frequency FSW 155 185 215 kHz RRF = 100k, TA = 25°C, VIN=8V, VOUT=1.1V, IOUT=10A 5
Switching Frequency FSW 185 215 245 kHz RRF = 39k, TA = 25°C, VIN=8V, VOUT=1.1V, IOUT=10A 5
Minimum On Time TON(MIN) 80 110 140 ns 5
Minimum Off Time TOFF(MIN) 350 450 550 ns VFB = 0.65V, VPHASE = -0.1V, OCSET = OPEN 5
Internal Soft-Start Time TSS 0.7 1 1.3 ms EN High to VOUT Regulation (95%) 5
UGATE Pull-Up Resistance 1.5 3 Ω BOOT-UGATE = 0.5V 5
UGATE Sink Resistance 0.7 1.8 Ω UGATE-PHASE = 0.5V 5
LGATE Pull-Up Resistance 1 2.2 Ω PVCC-LGATE = 0.5V 5
LGATE Sink Resistance 0.5 1.2 Ω LGATE-GND = 0.5V 5
Bootstrap Forward Voltage VF Ron 0.5 0.8 V VVCC - VBOOT-GND, IF = 10mA 5
Bootstrap Reverse Leakage IR 0.5 uA VBOOT-GND = 30V, VPHASE = 25V, VVCC = 5V 5
VCC POR Threshold Rising VVCC THR 4.2 4.35 4.45 V VSS POR Threshold 5
EN Voltage Threshold Enable 1.8 V Enable 5
EN Voltage Threshold Shutdown 0.5 V Shutdown 5
EN Leakage 0.1 1 uA EN = 0V 6
RF Setting Threshold Forced PWM Mode 1.8 V Forced PWM Mode 6
RF Setting Threshold PFM/PWM Auto Skip Mode 0.5 V PFM/PWM Auto Skip Mode 6
POK Threshold Rising VPOK 87 90 93 % POK in from Lower (POK Goes High) 6
POK Threshold Falling VPOK 120 125 130 % POK out from Normal (POK Goes Low) 6
POK Leakage Current IPOK 0.1 1 uA VPOK = 5V 6
POK Sink Current 2.5 7.5 mA VPOK = 0.5V 6
POK Enable Delay Time 1.4 2 2.6 ms EN High to POK High 6
IOCSET OCP Threshold IOCSET 9 10 11 uA IOCSET Sourcing 6
Current-Limit Threshold Setting Range VROCSET 0.24 1.6 V VOCSET-GND Voltage, Over All Temperature 6
Over Current-Limit Voltage VOCSET-GND-VGND-PHASE -10 0 10 mV VOCSET-GND=60mV 6
Zero Crossing Comparator Off Voltage VGND-PHASE -9.5 0.5 10.5 mV EN=3.3V 6
UVP Threshold VUV 60 70 80 % 6
UVP Enable Delay 1.4 2 2.6 ms EN High to UVP Workable 6
OVP Rising Threshold VOVR 120 125 130 % 6
Input Voltage VIN 1.8 32 V 4
VCC Supply Voltage VCC 4.5 5.5 V 4
Converter Output Voltage VOUT 0.7 5.5 V 4
Converter Output Current IOUT 25 A 4
Ambient Temperature TA -40 85 °C 4
Junction Temperature TJ -40 125 °C 4
VCC Supply Voltage to GND VCC -0.3 7 V VCC to GND 4
BOOT Supply Voltage to GND VBOOT-GND -0.3 35 V BOOT to GND 4
BOOT Supply Voltage to PHASE VBOOT -0.3 7 V BOOT to PHASE 4
All Other Pins Voltage -0.3 V POK, OCSET, EN, FB, and RF to GND; upper limit VCC+0.3 4
UGATE Voltage to PHASE Pulse Width <400ns -5 V UGATE to PHASE; upper limit VBOOT+0.3 4
UGATE Voltage to PHASE Pulse Width >400ns -0.3 V UGATE to PHASE; upper limit VBOOT+0.3 4
LGATE Voltage to GND Pulse Width <400ns -5 V LGATE to GND; upper limit VCC+0.3 4
LGATE Voltage to GND Pulse Width >400ns -0.3 V LGATE to GND; upper limit VCC+0.3 4
PHASE Voltage to GND Pulse Width <400ns VPHASE -5 35 V PHASE to GND 4
PHASE Voltage to GND Pulse Width >400ns VPHASE -1 32 V PHASE to GND 4
Maximum Junction Temperature TJ 150 °C 4
Storage Temperature TSTG -65 150 °C 4
Maximum Soldering Temperature, 10 Seconds TSDR 260 °C 4
Thermal Resistance Junction to Ambient θJA 55 °C/W 3mmx3mm TDFN-10, exposed pad soldered to PCB 4

CAD (KiCad official)

  • Symbol: TD1730
  • Footprint: Package_DFN_QFN:DFN-10-1EP_3x3mm_P0.5mm_EP1.55x2.48mm
  • 3D model: TDFN-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: td1730-etched.step / td1730-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); td1730.step / td1730.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Techcode Semicon datasheet (17 pp, sha256 be3f475cbbb945c7, retrieved 2026-11-07, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF