Loads on click. Unloads only if this page sits in the background.
Contents

README

markdown

TD1663

Techcode Semicon · DC-DC Converters · ESOP-8

TD1663 from Techcode Semicon, in a ESOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BOOT passive Bootstrap capacitor connection for the high-side MOSFET gate driver. Connect a 0.1 µF ceramic capacitor (X7R/X5R, ≥16 V) from BOOT to SW. Maximum BOOT-to-SW voltage is 6.5 V; internal bootstrap regulator refreshes the cap when the high-side MOSFET is off.
2 VIN power_in Input supply pin, 9 V to 60 V operating range (absolute max 65 V). Connect to the power supply and bypass capacitors CIN; the path from VIN to the high-frequency bypass cap and GND must be as short as possible.
3 EN input Enable input with internal pull-up current source. Enable threshold ~2 V (typ); pull below 1.2 V to disable, float or tie to VIN to enable. Absolute max 5 V to GND. Can be driven by an external resistor divider from VIN to set an adjustable input UVLO.
4 RT passive Resistor timing pin - sets switching frequency (200 kHz to 1 MHz) with a resistor to GND per RT(kΩ) = 42904 × fSW(kHz)^-1.088 (e.g. 49.9 kΩ ≈ 500 kHz). Held at a fixed voltage by an internal amplifier; must not be left floating or shorted to ground.
5 FB input Feedback input to the error amplifier. Internal reference is 0.75 V (typ); connect to the mid-point of an output resistor divider to set VOUT. Absolute max 7 V to GND; do not short to ground during operation.
6 PGOOD output Open-drain power-good flag. Requires a 10 kΩ to 100 kΩ pull-up to a logic rail or DC voltage; the voltage on PGOOD must never exceed 7 V. High-Z when FB is within +7%/-6% of VREF; pulled low when FB is above +9% or below -8% of VREF.
7 GND power_in System ground reference for the device. Tie to the ground plane along with the thermal pad; return path for CIN, COUT, and freewheel diode should be short and localized.
8 SW output Switching node - internally connected to the source of the integrated 150 mΩ high-side N-MOSFET. Connect to the power inductor and the anode of the external freewheeling Schottky diode. SW swing range -1 V to 60 V (abs max -0.3 V to VIN+0.3 V).
9 Thermal Pad passive Exposed thermal pad - major heat dissipation path for the die. Must be soldered to the PCB ground plane for both thermal performance and electrical grounding.

Key specifications

Parameter Value
Manufacturer Techcode Semicon
Package ESOP-8
Category PMIC
Pins 9

Ordering variants

  • TD1663M
  • TD1663MR

CAD (KiCad official)

  • Symbol: TD1663
  • Footprint: Package_SO:SOIC-8-1EP_3.9x4.9mm_P1.27mm_EP2.41x3.3mm
  • 3D model: ESOP-8 (KiCad packages3D, STEP)
  • 3D model files: td1663-etched.step / td1663-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); td1663.step / td1663.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Techcode Semicon datasheet (None pp, sha256 c30e4dc75b831edf, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads on click. Unloads only if this page sits in the background.

PCB Footprint

Open full view ↗
Loads on click. Unloads only if this page sits in the background.
Loads on click. Unloads only if this page sits in the background.
Download PDF