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TCKE805NA

Public Made by Adom

by adom

TOSHIBA Surge Suppressors, WSON-10-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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TCKE805NA

TOSHIBA · Surge Suppressors · WSON-10-EP(3x3)

TCKE805NA from TOSHIBA, in a WSON-10-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 dV/dT passive Rise time set input: a capacitor between dV/dT and GND sets the VOUT slew rate at turn-on (CdV/dT operating range 1 nF typ., 100 nF max per the Operating Ranges table).
2 EN/UVLO input Enable input (high = output ON, low = OFF) that also sets the UVLO trip point with external resistors; rated -0.3 to 18 V, must not be left open.
3 VIN power_in Supply input to the power switch and device supply, operating range 4.4 to 18.0 V.
4 VIN power_in Supply input to the power switch and device supply, operating range 4.4 to 18.0 V.
5 VIN power_in Supply input to the power switch and device supply, operating range 4.4 to 18.0 V.
6 VOUT power_out Output of the power switch, continuous output current 0 to 5.0 A.
7 VOUT power_out Output of the power switch, continuous output current 0 to 5.0 A.
8 VOUT power_out Output of the power switch, continuous output current 0 to 5.0 A.
9 EFET output Gate drive for an external blocking N-channel MOSFET for reverse current blocking, outputs VIN+4.9 V (typ.); can be left floating if unused.
10 ILIM passive Current limit set input: a resistor between ILIM and GND sets the current limit, RILIM operating range 20 to 300 kΩ.
11 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package WSON-10-EP(3x3)
Category TVS/Fuse/Board Level Protection
Pins 11

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN under voltage lockout threshold, rising VIN_UVLO 4 4.15 4.4 V VIN = 5V, RILIM = 20kΩ; min/max Ta = -40 to 85°C, typ Ta = 25°C 6
EN/UVLO threshold voltage, rising VENR 1 1.1 1.2 V VIN = 5V, RILIM = 20kΩ; min/max Ta = -40 to 85°C, typ Ta = 25°C 6
EN/UVLO threshold voltage, falling VENF 0.89 0.96 1.01 V VIN = 5V, RILIM = 20kΩ; min/max Ta = -40 to 85°C, typ Ta = 25°C 6
On resistance RON 28 38 mΩ IOUT = 1.5 A 6
Quiescent current (ON state) IQ 0.46 0.61 mA VEN = 3 V, RILIM = 120 kΩ, IOUT = 0 A 6
Quiescent current (OFF state) IQ(OFF) 33 48 μA EN = 0V 6
dV/dT discharge resistance RdV/dT 3 5 9 Ω VEN = 0 V, IdV/dT = 10 mA 6
EFET discharge resistance REFET 12 24 40 Ω VEN = 0 V, IEFET = 20 mA 6
Over voltage clamp VOVC 5.62 6.04 6.45 V VIN = 7 V, IOUT = 1 A 6
Overcurrent limit ILIM 4.44 5.15 5.87 A RILIM = 20 kΩ, VIN - VOUT = 1 V 6
Overcurrent limit ILIM 3.88 4.38 4.88 A RILIM = 24 kΩ, VIN - VOUT = 1 V 6
Overcurrent limit ILIM 2.7 3.06 3.41 A RILIM = 35.1 kΩ, VIN - VOUT = 1 V 6
Overcurrent limit ILIM 1.52 1.78 2.04 A RILIM = 62 kΩ, VIN - VOUT = 1 V 6
Overcurrent limit ILIM 0.76 0.96 1.16 A RILIM = 120 kΩ, VIN - VOUT = 1 V 6
Overcurrent limit ILIM 0.35 0.5 0.65 A RILIM = 250 kΩ, VIN - VOUT = 1 V 6
Short-circuit current limit ISCL 0.05 0.15 0.5 A Warranted by design; hard short less than 10 mΩ 6
Output ramp time tdV/dT 200 400 700 μs VEN↑ to VOUT become VIN*90%, CdV/dT = OPEN 7
Input voltage VIN 4.4 18 V 2
Output current IOUT 0 5 A Continuous output current 2
ILIM external resistance RILIM 20 300 kΩ 2
Control voltage VEN/UVLO 0 18 V 2
Operating ambient temperature range Ta_opr -40 85 °C 2
External capacitance CdV/dT 1 100 nF 2
Input voltage VIN -0.3 18 V Ta = 25°C 2
ILIM voltage VILIM -0.3 6 V Ta = 25°C 2
dV/dT voltage VdV/dT -0.3 6 V Ta = 25°C 2
Control voltage VEN/UVLO -0.3 18 V Ta = 25°C 2
Output voltage VOUT -0.3 18 V -0.3 to VIN + 0.3 or 18.0 V which is smaller; Ta = 25°C 2
External MOSFET voltage VEFET -0.3 30 V Ta = 25°C 2
Power dissipation PD 2.4 W Mounted on FR4 board 76.2mm114.3mm1.6mm, 4 layer; Ta = 25°C 2
Junction temperature Tj 150 °C Ta = 25°C 2
Storage temperature Tstg -55 150 °C Ta = 25°C 2
VIN UVLO hysteresis VIN_UVhyst 5 % VIN = 5V, RILIM = 20kΩ; Ta = 25°C 6
Thermal shut down threshold TSD 160 °C Tj 6
Thermal shut down hysteresis TSDH 20 °C Tj (Auto-retry Type) 6
VOUT on time tON 330 μs VEN↑ to IIN = 100 mA, 1 A resistive load at VOUT, CdV/dT = OPEN (Note5) 7
VOUT off time tOFF 1 μs VEN↓ to VEFET↓, CEFET = OPEN (Note5), TCKE805NA 7

CAD (KiCad official)

  • Symbol: TCKE805NA
  • Footprint: Package_SON:VSON-10-1EP_3x3mm_P0.5mm_EP1.2x2mm
  • 3D model: WSON-10-EP(3x3) (KiCad packages3D, STEP)
  • 3D model files: tcke805na-etched.step / tcke805na-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tcke805na.step / tcke805na.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (24 pp, sha256 61e8ce69aa4fdd96, retrieved 2026-10-24, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF