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TCAN1057AEVDRQ1

Public Made by Adom

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Texas Instruments CAN ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Contents

README

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TCAN1057AEVDRQ1

Texas Instruments · CAN ICs · SOIC-8

TCAN1057AEVDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 TXD input CAN transmit data input referenced to VIO, with integrated pull-up.
2 GND power_in Ground connection that must be connected to the PCB ground.
3 VCC power_in 5-V supply voltage for the CAN transceiver (absolute maximum -0.3 V to 6 V).
4 RXD output CAN receive data output referenced to VIO, only driven once VIO is present, tri-state when powered off.
5 VIO power_in I/O supply voltage for the integrated level shifter, to be connected to the controller's I/O voltage source (absolute maximum -0.3 V to 6 V).
6 CANL bidirectional Low-level CAN bus input/output line, with bus fault protection of ±58 V.
7 CANH bidirectional High-level CAN bus input/output line, with bus fault protection of ±58 V.
8 S input Silent mode control input with integrated pull-up, which can be driven by the controller or a static system voltage source.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category Communication Interface Chip/UART/485/232
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.3 6 V 4
I/O level shifter supply voltage VIO -0.3 6 V 4
CAN bus I/O voltage VBUS -58 58 V 4
Max differential voltage CANH-CANL VDIFF -45 45 V 4
Logic input terminal voltage VLogic_Input -0.3 6 V 4
RXD output terminal voltage VRXD -0.3 6 V 4
RXD output current IO(RXD) -8 8 mA 4
Junction temperature TJ -40 175 °C 4
Storage temperature TSTG -65 150 °C 4
Supply voltage VCC 4.5 5 5.5 V 5
Supply voltage for I/O level shifter VIO 1.7 5.5 V 5
RXD high-level output current IOH(RXD) -1.5 mA 5
RXD low-level output current IOL(RXD) 1.5 mA 5
Operating ambient temperature TA -40 150 ℃ 5
Junction-to-ambient thermal resistance RθJA 127.5 ℃/W D (SOIC) 5
Junction-to-case (top) thermal resistance RθJC(top) 67.6 ℃/W D (SOIC) 5
Junction-to-board thermal resistance RθJB 70.9 ℃/W D (SOIC) 5
Junction-to-top characterization parameter ΨJT 19.3 ℃/W D (SOIC) 5
Junction-to-board characterization parameter ΨJB 70.2 ℃/W D (SOIC) 5
Supply current, normal mode dominant ICC 45 70 mA TXD = 0 V, S = 0 V, RL = 60 Ω, CL = open 5
Supply current, normal mode dominant ICC 49 80 mA TXD = 0 V, S = 0 V, RL = 50 Ω, CL = open 5
Supply current, normal mode recessive ICC 4.5 7.5 mA TXD = VIO, S = 0 V, RL = 50 Ω, CL = open 5
Supply current, dominant with bus fault ICC 130 mA TXD = 0 V, S = 0 V, CANH = CANL = ±25 V, RL = open, CL = open 5
Supply current, silent mode ICC 2.1 mA TXD = S = VIO, RL = 50 Ω, CL = open 5
I/O supply current, dominant IIO 125 300 µA S = 0 V, TXD = 0 V, RXD floating 5
I/O supply current, recessive IIO 25 48 µA TXD = VIO, S = 0 V, RXD floating 5
Rising undervoltage detection on VCC UVCC 4.2 4.4 V protected mode 5
Falling undervoltage detection on VCC UVCC 3.5 4 4.25 V protected mode 5
Hysteresis voltage on UVCC VHYS(UVCC) 200 mV 5
Rising undervoltage detection on VIO UVVIO 1.56 1.65 V 5
Falling undervoltage detection on VIO UVVIO 1.4 1.51 1.59 V 5
Hysteresis voltage on UVIO VHYS(UVIO) 40 mV 5
Thermal shutdown temperature TTSD 175 195 210 °C 6
Thermal shutdown hysteresis TTSD(HYS) 12 °C 6
Dominant output voltage CANH VO(DOM) 2.75 4.5 V S = 0 V, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 6
Dominant output voltage CANL VO(DOM) 0.5 2.25 V S = 0 V, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 6
Recessive output voltage VO(REC) 2 3 V S = 0 V, TXD = VIO, RL = open (no load), RCM = open 6
Driver symmetry VSYM 0.9 1.1 V/V S = 0 V, TXD = 250 kHz, 1 MHz, 2.5 MHz, RL = 60 Ω, CSPLIT = 4.7 nF, CL = open, RCM = open 6
DC output symmetry VSYM_DC -400 400 mV S = 0 V, RL = 60 Ω, CL = open 6
Differential output voltage, dominant VOD(DOM) 1.5 3 V S = 0 V, TXD = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open 6
Differential output voltage, dominant VOD(DOM) 1.4 3.3 V S = 0 V, TXD = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open 6
Differential output voltage, dominant VOD(DOM) 1.5 5 V S = 0 V, TXD = 0 V, RL = 2240 Ω, CL = open 6
Differential output voltage, recessive VOD(REC) -120 12 mV S = 0 V, TXD = VIO, RL = 60 Ω, CL = open 6
Differential output voltage, recessive VOD(REC) -50 50 mV S = 0 V, TXD = VIO, RL = open, CL = open 6
Short-circuit output current, dominant IOS(SS_DOM) -115 mA S = 0 V, TXD = 0 V, V(CANH) = -15 V to 40 V, CANL = open 7
Short-circuit output current, dominant IOS(SS_DOM) 115 mA S = 0 V, TXD = 0 V, V(CAN_L) = -15 V to 40 V, CANH = open 7
Short-circuit output current, recessive IOS(SS_REC) -5 5 mA S = 0 V, TXD = VIO, -27 V ≤ VBUS ≤ 32 V 7
Input threshold voltage VIT 500 900 mV S = 0 V, -12 V ≤ VCM ≤ 12 V 7
Dominant state differential input voltage range VDOM 0.9 9 V S = 0 V, -12 V ≤ VCM ≤ 12 V 7
Recessive state differential input voltage range VREC -4 0.5 V S = 0 V, -12 V ≤ VCM ≤ 12 V 7
Hysteresis voltage for input threshold VHYS 115 mV S = 0 V, -12 V ≤ VCM ≤ 12 V 7
Common-mode range VCM -12 12 V Normal and silent mode 7
Unpowered bus input leakage current ILKG(IOFF) 5 µA CANH = CANL = 5 V, VCC = VIO = GND 7
Differential input resistance RID 40 90 kΩ TXD = VIO, S = 0 V, -12 V ≤ VCM ≤ 12 V 7
Single-ended input resistance RIN 20 45 kΩ 7
Input resistance matching RIN(M) -1 1 % V(CAN_H) = V(CAN_L) = 5 V 7
TXD high-level input leakage current IIH -2.5 0 1 µA TXD = VCC = VIO = 5.5 V 7
TXD low-level input leakage current IIL -200 -100 -20 µA TXD = 0 V, VCC = VIO = 5.5 V 7
Total loop delay recessive to dominant tPROP(LOOP1) 125 210 ns S = 0 V, VIO = 2.8 V to 5.5 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 8
Total loop delay dominant to recessive tPROP(LOOP2) 150 210 ns S = 0 V, VIO = 2.8 V to 5.5 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF 8
Dominant timeout tTXD_DTO 1.2 4 ms S = 0 V, RL = 60 Ω, CL = 100 pF 8
Mode change time tMODE 20 µs normal to silent or silent to normal 8

CAD (KiCad official)

  • Symbol: TCAN1057AEVDRQ1
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tcan1057aevdrq1-etched.step / tcan1057aevdrq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tcan1057aevdrq1.step / tcan1057aevdrq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (28 pp, sha256 9433bf766a8ca50e, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF