# TCAN1051VDRQ1

**Texas Instruments** · CAN ICs · SOIC-8

TCAN1051VDRQ1 from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | TXD | input | CAN transmit data input, LOW for dominant and HIGH for recessive bus states. |
| 2 | GND | power_in | Ground connection. |
| 3 | VCC | power_in | Transceiver 5-V supply voltage, operating range 4.5 V to 5.5 V. |
| 4 | RXD | output | CAN receive data output, LOW for dominant and HIGH for recessive bus states, driven to VIO on this V-suffix device. |
| 5 | VIO | power_in | Transceiver I/O level-shifting supply voltage for devices with the V suffix, designed for 3.0 V to 5.5 V. |
| 6 | CANL | bidirectional | Low-level CAN bus input/output line, bus fault protected to ±58 V for non-H variants. |
| 7 | CANH | bidirectional | High-level CAN bus input/output line, bus fault protected to ±58 V for non-H variants. |
| 8 | S | input | Silent mode control input, active high. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Interface ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 5-V Bus Supply Voltage Range | VCC | 4.5 |  | 5.5 | V |  | 7 |
| I/O Level-Shifting Voltage Range | VIO | 2.8 |  | 5.5 | V |  | 7 |
| RXD high level output current | IOH(RXD) | -2 |  |  | mA |  | 7 |
| RXD low level output current | IOL(RXD) |  |  | 2 | mA |  | 7 |
| 5-V Bus Supply Voltage Range | VCC | -0.3 |  | 7 | V | All Devices | 5 |
| I/O Level-Shifting Voltage Range | VIO | -0.3 |  | 7 | V | Devices with the V suffix | 5 |
| CAN Bus I/O voltage range | VBUS | -58 |  | 58 | V | CANH, CANL; Devices without the H suffix | 5 |
| Max differential voltage between CANH and CANL | V(Diff) | -58 |  | 58 | V | Devices without the H suffix | 5 |
| Logic input terminal voltage range | V(Logic_Input) | -0.3 |  | 7 | V | TXD, S; +7 and VI ≤ VIO + 0.3 V | 5 |
| Logic output terminal voltage range | V(Logic_Output) | -0.3 |  | 7 | V | RXD; +7 and VI ≤ VIO + 0.3 V | 5 |
| RXD output current | IO(RXD) | -8 |  | 8 | mA |  | 5 |
| Virtual junction temperature range | TJ | -55 |  | 150 | °C |  | 5 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 5 |
| HBM ESD, CAN bus terminals to GND |  | -16000 |  | 16000 | V | D (SOIC) package, CANH, CANL to GND | 5 |
| CDM ESD, all terminals |  | -1500 |  | 1500 | V | D (SOIC) package | 5 |
| Junction-to-air thermal resistance | RθJA |  | 105.8 |  | °C/W | D (SOIC), High-K | 7 |
| Junction-to-board thermal resistance | RθJB |  | 46.8 |  | °C/W | D (SOIC) | 7 |
| Junction-to-case (top) thermal resistance | RθJC(TOP) |  | 48.3 |  | °C/W | D (SOIC) | 7 |
| Thermal shutdown temperature | TTSD |  | 170 |  | °C |  | 7 |
| Thermal shutdown hysteresis | TTSD_HYS |  | 5 |  | °C |  | 7 |
| 5-V supply current, normal mode dominant | ICC |  | 40 | 70 | mA | TXD = 0 V, RL = 60 Ω, CL = open, RCM = open, S = 0V | 8 |
| 5-V supply current, normal mode dominant | ICC |  | 45 | 80 | mA | TXD = 0 V, RL = 50 Ω, CL = open, RCM = open, S = 0V | 8 |
| 5-V supply current, dominant bus fault | ICC |  |  | 180 | mA | TXD = 0 V, S = 0V, CANH = -12V, RL = open, CL = open, RCM = open | 8 |
| 5-V supply current, normal mode recessive | ICC |  | 1.5 | 2.5 | mA | TXD = VCC, RL = 50 Ω, CL = open, RCM = open, S = 0V | 8 |
| 5-V supply current, silent mode | ICC |  | 1.5 | 2.5 | mA | TXD = VCC, RL = 50 Ω, CL = open, RCM = open, S = VCC | 8 |
| I/O supply current | IIO |  | 90 | 300 | µA | RXD Floating, TXD = S = 0 or 5.5 V | 8 |
| Rising undervoltage detection on VCC | UVVCC |  | 4.2 | 4.4 | V | All devices, protected mode | 8 |
| Falling undervoltage detection on VCC | UVVCC | 3.8 | 4 | 4.25 | V | protected mode | 8 |
| Hysteresis voltage on UVVCC | VHYS(UVVCC) |  | 200 |  | mV |  | 8 |
| Undervoltage detection on VIO | UVVIO | 1.3 |  | 2.75 | V | Devices with the V suffix, protected mode | 8 |
| Hysteresis voltage on UVVIO | VHYS(UVVIO) |  | 80 |  | mV | protected mode | 8 |
| S high-level input leakage current | IIH |  |  | 30 | µA | S = VCC or VIO = 5.5 V | 8 |
| S low-level input leakage current | IIL | -2 | 0 | 2 | µA | S = 0 V, VCC = VIO = 5.5 V | 8 |
| S unpowered leakage current | Ilkg(OFF) | -1 |  | 1 | µA | S = 5.5 V, VCC = VIO = 0 V | 8 |
| TXD high-level input leakage current | IIH | -2.5 | 0 | 1 | µA | TXD = VCC = VIO = 5.5 V | 8 |
| TXD low-level input leakage current | IIL | -100 | -25 | -7 | µA | TXD = 0 V, VCC = VIO = 5.5 V | 8 |
| TXD unpowered leakage current | Ilkg(OFF) | -1 | 0 | 1 | µA | TXD = 5.5 V, VCC = VIO = 0 V | 8 |
| TXD input capacitance | CI |  | 5 |  | pF | VIN = 0.4 * sin(4E6 * π * t) + 2.5 V | 8 |
| RXD unpowered leakage current | Ilkg(OFF) | -1 | 0 | 1 | µA | RXD = 5.5 V, VCC = 0 V, VIO = 0 V | 9 |
| Bus output voltage dominant, CANH | VO(DOM) | 2.75 |  | 4.5 | V | TXD = 0 V, S = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open | 9 |
| Bus output voltage dominant, CANL | VO(DOM) | 0.5 |  | 2.25 | V | TXD = 0 V, S = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open | 9 |
| Bus output voltage recessive, CANH and CANL | VO(REC) | 2 |  | 3 | V | TXD = VCC, VIO = VCC, S = VCC or 0 V, RL = open (no load), RCM = open | 9 |
| Differential output voltage dominant | VOD(DOM) | 1.4 |  | 3 | V | TXD = 0 V, S = 0 V, 45 Ω ≤ RL < 50 Ω, CL = open, RCM = open | 9 |
| Differential output voltage dominant | VOD(DOM) | 1.5 |  | 3 | V | TXD = 0 V, S = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open | 9 |
| Differential output voltage dominant | VOD(DOM) | 1.5 |  | 5 | V | TXD = 0 V, S = 0 V, RL = 2240 Ω, CL = open, RCM = open | 9 |
| Differential output voltage recessive | VOD(REC) | -120 |  | 12 | mV | TXD = VCC, S = 0 V, RL = 60 Ω, CL = open, RCM = open | 9 |
| Differential output voltage recessive | VOD(REC) | -50 |  | 50 | mV | TXD = VCC, S = 0 V, RL = open (no load), CL = open, RCM = open | 9 |
| Transient symmetry | VSYM | 0.9 |  | 1.1 | V/V | S at 0 V, Rterm = 60 Ω, Csplit = 4.7 nF, CL = open, RCM = open, TXD = 250 kHz, 1 MHz | 9 |
| DC output symmetry | VSYM_DC | -0.4 |  | 0.4 | V | S = 0 V, RL = 60 Ω, CL = open, RCM = open | 9 |
| Short-circuit steady-state output current, dominant (CANH) | IOS(SS_DOM) | -100 |  |  | mA | S at 0 V, VCANH = -5 V to 40 V, CANH = open, TXD = 0 V | 9 |
| Short-circuit steady-state output current, dominant (CANL) | IOS(SS_DOM) |  |  | 100 | mA | S at 0 V, VCANL = -5 V to 40 V, CANH = open, TXD = 0 V | 9 |
| Short-circuit steady-state output current, recessive | IOS(SS_REC) | -5 |  | 5 | mA | -27 V ≤ VBUS ≤ 32 V, VBUS = CANH = CANL, TXD = VCC, all modes | 9 |
| Common mode range, normal mode | VCM | -30 |  | 30 | V | S = 0 or VCC or VIO | 10 |
| Positive-going input threshold voltage | VIT+ |  |  | 900 | mV | -20 V ≤ VCM ≤ +20 V, all modes | 10 |
| Negative-going input threshold voltage | VIT- | 500 |  |  | mV | -20 V ≤ VCM ≤ +20 V, all modes | 10 |
| Positive-going input threshold voltage | VIT+ |  |  | 1000 | mV | -30 V ≤ VCM ≤ +30 V, all modes | 10 |
| Negative-going input threshold voltage | VIT- | 400 |  |  | mV | -30 V ≤ VCM ≤ +30 V, all modes | 10 |
| Hysteresis voltage (VIT+ - VIT-) | VHYS |  | 120 |  | mV | S = 0 or VCC or VIO | 10 |
| Power-off bus input leakage current | Ilkg(IOFF) |  |  | 4.8 | µA | CANH = CANL = 5 V, VCC = VIO = 0 V | 10 |
| Input capacitance to ground (CANH or CANL) | CI |  | 24 | 30 | pF | TXD = VCC, VIO = VCC | 10 |
| Differential input capacitance | CID |  | 12 | 15 | pF | TXD = VCC, VIO = VCC | 10 |
| Differential input resistance | RID | 30 |  | 80 | kΩ | TXD = VCC = VIO = 5 V, S = 0 V, -30 V ≤ VCM ≤ +30 V | 10 |
| Input resistance (CANH or CANL) | RIN | 15 |  | 40 | kΩ | TXD = VCC = VIO = 5 V, S = 0 V, -30 V ≤ VCM ≤ +30 V | 10 |
| Input resistance matching | RIN(M) | -2 |  | 2 | % | VCANH = VCANL = 5 V | 10 |
| Total loop delay, recessive to dominant | tPROP(LOOP1) |  | 100 | 160 | ns | S = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF | 11 |
| Total loop delay, dominant to recessive | tPROP(LOOP2) |  | 110 | 175 | ns | S = 0 V, RL = 60 Ω, CL = 100 pF, CL(RXD) = 15 pF | 11 |

## CAD (KiCad official)

- Symbol: `TCAN1051VDRQ1`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tcan1051vdrq1-etched.step` / `tcan1051vdrq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tcan1051vdrq1.step` / `tcan1051vdrq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/tcan1051vdrq1.pdf) (38 pp, sha256 `278fa55a84e0683e`, retrieved 2026-10-26, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tcan1051vdrq1-datasheet.pdf)