component
TCA6424RGJR
Public Made by Adomby adom
Texas Instruments I/O Expanders, UQFN-32(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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TCA6424RGJR
Texas Instruments · I/O Expanders · UQFN-32(5x5)
TCA6424RGJR from Texas Instruments, in a UQFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P00 | bidirectional | P-port input/output (push-pull design structure); at power on, P00 is configured as an input. |
| 2 | P01 | bidirectional | P-port input/output (push-pull design structure); at power on, P01 is configured as an input. |
| 3 | P02 | bidirectional | P-port input/output (push-pull design structure); at power on, P02 is configured as an input. |
| 4 | P03 | bidirectional | P-port input/output (push-pull design structure); at power on, P03 is configured as an input. |
| 5 | P04 | bidirectional | P-port input/output (push-pull design structure); at power on, P04 is configured as an input. |
| 6 | P05 | bidirectional | P-port input/output (push-pull design structure); at power on, P05 is configured as an input. |
| 7 | P06 | bidirectional | P-port input/output (push-pull design structure); at power on, P06 is configured as an input. |
| 8 | P07 | bidirectional | P-port input/output (push-pull design structure); at power on, P07 is configured as an input. |
| 9 | P10 | bidirectional | P-port input/output (push-pull design structure); at power on, P10 is configured as an input. |
| 10 | P11 | bidirectional | P-port input/output (push-pull design structure); at power on, P11 is configured as an input. |
| 11 | P12 | bidirectional | P-port input/output (push-pull design structure); at power on, P12 is configured as an input. |
| 12 | P13 | bidirectional | P-port input/output (push-pull design structure); at power on, P13 is configured as an input. |
| 13 | P14 | bidirectional | P-port input/output (push-pull design structure); at power on, P14 is configured as an input. |
| 14 | P15 | bidirectional | P-port input/output (push-pull design structure); at power on, P15 is configured as an input. |
| 15 | P16 | bidirectional | P-port input/output (push-pull design structure); at power on, P16 is configured as an input. |
| 16 | P17 | bidirectional | P-port input/output (push-pull design structure); at power on, P17 is configured as an input. |
| 17 | P20 | bidirectional | P-port input/output (push-pull design structure); at power on, P20 is configured as an input. |
| 18 | P21 | bidirectional | P-port input/output (push-pull design structure); at power on, P21 is configured as an input. |
| 19 | P22 | bidirectional | P-port input/output (push-pull design structure); at power on, P22 is configured as an input. |
| 20 | P23 | bidirectional | P-port input/output (push-pull design structure); at power on, P23 is configured as an input. |
| 21 | P24 | bidirectional | P-port input/output (push-pull design structure); at power on, P24 is configured as an input. |
| 22 | P25 | bidirectional | P-port input/output (push-pull design structure); at power on, P25 is configured as an input. |
| 23 | P26 | bidirectional | P-port input/output (push-pull design structure); at power on, P26 is configured as an input. |
| 24 | P27 | bidirectional | P-port input/output (push-pull design structure); at power on, P27 is configured as an input. |
| 25 | GND | power_in | Ground. |
| 26 | ADDR | input | Address input; connect directly to VCCP or ground. |
| 27 | VCCP | power_in | Supply voltage of TCA6424 for P port, 1.65 V to 5.5 V recommended. |
| 28 | RESET | input | Active-low reset input; connect to VCCP through a pullup resistor if no active connection is used. |
| 29 | SCL | input | Serial clock bus; connect to VCCI through a pullup resistor. |
| 30 | SDA | bidirectional | Serial data bus; connect to VCCI through a pullup resistor. |
| 31 | VCCI | power_in | Supply voltage of I2C bus (1.65 V to 5.5 V); connect directly to the VCC of the external I2C master, provides voltage-level translation. |
| 32 | INT | output | Open-drain interrupt output; connect to VCCI through a pullup resistor. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | UQFN-32(5x5) |
| Category | Communication Interface Chip |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage VCCI | VCCI | 1.65 | 5.5 | V | 5 | ||
| Supply voltage VCCP | VCCP | 1.65 | 5.5 | V | 5 | ||
| Operating free-air temperature | TA | -40 | 85 | °C | 5 | ||
| High-level output current P27-P00 | IOH | 10 | mA | P27-P00 | 5 | ||
| Low-level output current P27-P00 | IOL | 25 | mA | P27-P00 | 5 | ||
| Supply voltage range VCCI | VCCI | -0.5 | 6.5 | V | 5 | ||
| Supply voltage range VCCP | VCCP | -0.5 | 6.5 | V | 5 | ||
| Input voltage range | VI | -0.5 | 6.5 | V | 5 | ||
| Output voltage range | VO | -0.5 | 6.5 | V | 5 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 5 | ||
| Package thermal impedance | θJA | 50.05 | °C/W | RGJ package | 5 | ||
| Input diode clamp voltage | VIK | -1.2 | V | II = -18 mA, VCCP 1.65 V to 5.5 V | 6 | ||
| Power-on reset voltage | VPOR | 1 | 1.4 | V | VI = VCCP or GND, IO = 0 | 6 | |
| SDA low-level output current | IOL | 3 | mA | SDA VOL = 0.4 V | 6 | ||
| INT low-level output current | IOL | 3 | 15 | mA | INT VOL = 0.4 V | 6 | |
| Input leakage SCL, SDA | II | -0.1 | 0.1 | μA | VI = VCCI or GND | 6 | |
| Input leakage ADDR, RESET | II | -0.1 | 0.1 | μA | VI = VCCP or GND | 6 | |
| P port input high current | IIH | 1 | μA | VI = VCCP | 6 | ||
| P port input low current | IIL | 1 | μA | VI = GND | 6 | ||
| Operating supply current | ICC | 8 | 30 | μA | fSCL = 400 kHz, IO = 0, I/O = inputs | 6 | |
| Operating supply current | ICC | 1.7 | 10 | μA | fSCL = 100 kHz, IO = 0, I/O = inputs | 6 | |
| Standby supply current | ICC | 0.1 | 2 | μA | fSCL = 0, IO = 0, I/O = inputs | 6 | |
| Additional standby current ΔICCP | ΔICCP | 60 | μA | One input at VCCP, 0.6 V, other inputs at VCCP or GND | 6 | ||
| Additional standby current ΔICCI | ΔICCI | 25 | μA | One input at VCCI, 0.6 V, other inputs at VCCI or GND | 6 | ||
| Input capacitance SCL | CI | 6 | 7 | pF | VI = VCCI or GND | 6 | |
| I/O capacitance SDA | Cio | 7 | 8 | pF | VIO = VCCI or GND | 6 | |
| I/O capacitance P port | Cio | 7.5 | 8.5 | pF | VIO = VCCP or GND | 6 | |
| I2C clock frequency (fast mode) | fscl | 0 | 400 | kHz | Fast mode | 7 | |
| Reset time | tRESET | 600 | ns | 7 | |||
| Output data valid | tPV | 400 | ns | SCL to P27-P00, CL ≤ 100 pF | 7 | ||
| Voltage trip point of POR on falling VCC | VPORF | 0.767 | 1.144 | V | TA = -40°C to 85°C | 28 | |
| Voltage trip point of POR on rising VCC | VPORR | 1.033 | 1.428 | V | TA = -40°C to 85°C | 28 |
CAD (KiCad official)
- Symbol:
TCA6424RGJR - Footprint:
Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm - 3D model: UQFN-32(5x5) (KiCad packages3D, STEP)
- 3D model files:
tca6424rgjr-etched.step/tca6424rgjr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tca6424rgjr.step/tca6424rgjr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (37 pp, sha256
076b529753c2066c, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).