component
TC9402CPD
Public Made by Adomby adom
Microchip Tech Voltage-to-Frequency / Frequency-to-Voltage Converters, PDIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
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| tc9402cpd-etched.step | 6d ago |
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TC9402CPD
Microchip Tech · Voltage-to-Frequency / Frequency-to-Voltage Converters · PDIP-14
TC9402CPD from Microchip Tech, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | IBIAS | passive | Sets the bias current in the device; connect to VSS through a 100 kΩ resistor (RBIAS = 100 kΩ ±10% for specifications). |
| 2 | ZERO ADJ | input | Low frequency adjustment input; non-inverting input of the operational amplifier that sets the low frequency set point. |
| 3 | IIN | input | Input current connection (inverting input/summing junction of the op amp) for the V/F converter; 10 µA full-scale specified, over-range up to 50 µA usable. |
| 4 | VSS | power_in | Negative power supply voltage connection, typically -5V (operating range -4V to -7.5V). |
| 5 | VREF OUT | power_in | Reference capacitor (CREF) connection through which the charging current for CREF is supplied. |
| 6 | GND | power_in | Analog ground. |
| 7 | VREF | power_in | Voltage reference input, typically -5V, requiring a low-impedance source with a 0.1 µF bypass capacitor to ground. |
| 8 | PULSE FREQ OUT | output | Open-drain N-channel frequency output that pulses LOW each time the threshold detector limit is reached, with pulse rate proportional to input voltage; requires a pull-up resistor. |
| 9 | OUTPUT COMMON | passive | Source connection for the open-drain output FETs (PULSE FREQ OUT and FREQ/2 OUT). |
| 10 | FREQ/2 OUT | output | Open-drain square-wave output at one-half the frequency of the pulse output (pin 8), transitioning on the rising edge of pin 8; requires a pull-up resistor. |
| 11 | THRESHOLD DETECTOR | input | Input to the threshold detector (nominal threshold (VDD+VSS)/2 ±400 mV); the frequency input in F/V operation and connected to AMPLIFIER OUT in V/F mode. |
| 12 | AMPLIFIER OUT | output | Output of the integrator amplifier, with a negative-going ramp in V/F mode and a voltage proportional to input frequency in F/V mode. |
| 13 | NC | unconnected | No internal connection. |
| 14 | VDD | power_in | Positive power supply connection, typically +5V (operating range +4V to +7.5V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-14 |
| Category | ADC/DAC/Data Conversion |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Linearity 10 kHz Full Scale | 0.05 | 0.25 | % | V/F, Output Deviation from Straight Line Between Normalized Zero and Full Scale Input | 3 | ||
| Linearity 100 kHz Full Scale | 0.25 | 0.5 | % | V/F, Output Deviation from Straight Line Between Normalized Zero Reading and Full Scale Input | 3 | ||
| Gain Temperature Drift | -100 | 50 | 100 | ppm/°C | Full Scale, Variation in Gain A due to Temperature Change (Note 1) | 3 | |
| Zero Offset | -100 | 20 | 100 | mV | Correction at Zero Adjust for Zero Output when Input is Zero (Note 2) | 3 | |
| Zero Temperature Drift | -100 | 50 | 100 | µV/°C | Variation in Zero Offset Due to Temperature Change (Note 1) | 3 | |
| IIN Over Range | 50 | µA | Over Range Current | 4 | |||
| VSAT @ IOL = 10mA | VSAT | 0.2 | 0.4 | V | Logic "0" Output Voltage (Note 3) | 4 | |
| VOUTMAX, VOUT Common | VOUTMAX, VOUT | 18 | V | Voltage Range Between Output and Common (Note 4) | 4 | ||
| IDD Quiescent (F/V) | IDD | 3 | 10 | mA | Current Required from Positive Supply during Operation (Note 5) | 4 | |
| ISS Quiescent (F/V) | ISS | -3 | -10 | mA | Current Required from Negative Supply during Operation (Note 5) | 4 | |
| VDD Supply (F/V) | VDD | 4 | 7.5 | V | Operating Range of Positive Supply | 4 | |
| VSS Supply (F/V) | VSS | -4 | -7.5 | V | Operating Range of Negative Supply | 4 | |
| VREF, VSS (F/V) | VREF, VSS | -2.5 | V | Range of Voltage Reference Input | 4 | ||
| Non-Linearity (F/V) | 0.05 | 0.25 | % | Full Scale, Deviation from ideal Transfer Function (Note 10) | 4 | ||
| Frequency Input Positive Excursion | 0.4 | V | Voltage Required to Turn Threshold Detector On | 5 | |||
| Frequency Input Negative Excursion | -0.4 | -2 | V | Voltage Required to Turn Threshold Detector Off | 5 | ||
| Output Loading | 2 | kΩ | Resistive Loading at Output of Op Amp | 5 | |||
| IDD Quiescent (analog) | IDD | 3 | 10 | mA | Current Required from Positive Supply During Operation (Note 10) | 5 | |
| ISS Quiescent (analog) | ISS | -3 | -10 | mA | Current Required from Negative Supply During Operation (Note 10) | 5 | |
| VDD Supply | VDD | 4 | 7.5 | V | Operating Range of Positive Supply | 5 | |
| VSS Supply | VSS | -4 | -7.5 | V | Operating Range of Negative Supply | 5 | |
| VREF, VSS | VREF, VSS | -2.5 | V | Range of Voltage Reference Input | 5 | ||
| Gain Variance | 10 | % of Nominal | Variation from Ideal Accuracy, printed ±10 | 3 | |||
| IIN Full Scale | 10 | µA | Full Scale Analog Input Current to achieve Specified Accuracy | 4 | |||
| Response Time | 2 | Cycle | Settling Time to 0.1% Full Scale | 4 | |||
| Pulse Frequency Output Width | 3 | µs | 4 | ||||
| Minimum Positive Pulse Width | 5 | μs | Time between Threshold Crossings (Note 8) | 5 | |||
| Minimum Negative Pulse Width | 0.5 | μs | Time Between Threshold Crossings (Note 8) | 5 | |||
| Input Impedance | 10 | MΩ | 5 | ||||
| Supply voltage VDD, VSS | VDD, VSS | 18 | V | 3 | |||
| Input current IIN | IIN | 10 | mA | 3 | |||
| VREF, VSS | VREF, VSS | -1.5 | V | 3 | |||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| Operating Temperature Range, C Device | 0 | 70 | °C | C Device | 3 |
CAD (KiCad official)
- Symbol:
TC9402CPD - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files:
tc9402cpd-etched.step/tc9402cpd-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc9402cpd.step/tc9402cpd.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (28 pp, sha256
4a8d279f0b7aa143, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).