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TC7SZ08FU

Public Made by Adom

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TOSHIBA(东芝) Logic Gates, SOT-353. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TC7SZ08FU

TOSHIBA(东芝) · Logic Gates · SOT-353

TC7SZ08FU from TOSHIBA(东芝), in a SOT-353. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 IN B input Gate input B of the 2-input AND gate; 5.5 V tolerant input, unused inputs must be tied to VCC or GND.
2 IN A input Gate input A of the 2-input AND gate; 5.5 V tolerant input, unused inputs must be tied to VCC or GND.
3 GND power_in Ground pin (0 V reference).
4 OUT Y output AND gate output Y, high only when A and B are both high; 5.5 V power-down protection output with ±24 mA (min) drive at VCC = 3.0 V.
5 VCC power_in Supply voltage pin, operating range 1.65 to 5.5 V (absolute maximum -0.5 to 6.0 V).

Key specifications

Parameter Value
Manufacturer TOSHIBA(东芝)
Package SOT-353
Category Logic
Pins 5

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC 1.65 5.5 V 3
Supply voltage (data retention) VCC 1.5 5.5 V Data retention only (Note 1) 3
Input voltage VIN 0 5.5 V 3
Output voltage VOUT 0 5.5 V VCC = 0 V (Note 2) 3
Output voltage (high or low state) VOUT 0 V Upper limit is VCC; H or L state (Note 3) 3
Operating temperature Topr -40 85 °C Devices other than J(CT suffix (Note 5)) 3
Input rise and fall time dt/dv 0 20 ns/V VCC = 1.8 ± 0.15 V, 2.5 ± 0.2 V 3
Input rise and fall time dt/dv 0 10 ns/V VCC = 3.3 ± 0.3 V 3
Input rise and fall time dt/dv 0 5 ns/V VCC = 5.0 ± 0.5 V 3
Supply voltage VCC -0.5 6 V 2
Input voltage VIN -0.5 6 V 2
DC output voltage VOUT -0.5 6 V 2
Input diode current IIK -20 mA 2
Output diode current IOK -20 mA 2
DC output current IOUT -50 50 mA 2
VCC/ground current ICC -50 50 mA 2
Power dissipation PD 200 mW 2
Storage temperature Tstg -65 150 °C 2
High-level input voltage (min = VCC × 0.88) VIH 0.88 ×VCC VCC = 1.65 to 1.95 V 4
High-level input voltage (min = VCC × 0.75) VIH 0.75 ×VCC VCC = 2.3 to 5.5 V 4
Low-level input voltage (max = VCC × 0.12) VIL 0.12 ×VCC VCC = 1.65 to 1.95 V 4
Low-level input voltage (max = VCC × 0.25) VIL 0.25 ×VCC VCC = 2.3 to 5.5 V 4
High-level output voltage VOH 1.55 V IOH = -100 µA; VCC = 1.65 V 4
High-level output voltage VOH 2.2 V IOH = -100 µA; VCC = 2.3 V 4
High-level output voltage VOH 2.9 V IOH = -100 µA; VCC = 3.0 V 4
High-level output voltage VOH 4.4 V IOH = -100 µA; VCC = 4.5 V 4
High-level output voltage VOH 1.9 V IOH = -8 mA; VCC = 2.3 V 4
High-level output voltage VOH 2.4 V IOH = -16 mA; VCC = 3.0 V 4
High-level output voltage VOH 2.3 V IOH = -24 mA; VCC = 3.0 V 4
High-level output voltage VOH 3.8 V IOH = -32 mA; VCC = 4.5 V 4
Low-level output voltage VOL 0.1 V IOL = 100 µA; VCC = 1.65 V 4
Low-level output voltage VOL 0.3 V IOL = 8 mA; VCC = 2.3 V 4
Low-level output voltage VOL 0.4 V IOL = 16 mA; VCC = 3.0 V 4
Low-level output voltage VOL 0.55 V IOL = 24 mA; VCC = 3.0 V 4
Input leakage current IIN -10 10 µA VIN = 5.5 V or GND; VCC = 0 to 5.5 V 4
Power-OFF leakage current IOFF 10 µA VIN or VOUT = 5.5 V; VCC = 0 V 4
Quiescent supply current ICC 20 µA VIN = VCC or GND; VCC = 5.5 V 4
Propagation delay time tPLH,tPHL 2 5.2 10 ns Ta = 25 °C; RL = 1 MΩ, CL = 15 pF; VCC = 1.8 ± 0.15 V 6
Propagation delay time tPLH,tPHL 0.8 3.4 7 ns Ta = 25 °C; RL = 1 MΩ, CL = 15 pF; VCC = 2.5 ± 0.2 V 6
Propagation delay time tPLH,tPHL 0.5 2.6 4.7 ns Ta = 25 °C; RL = 1 MΩ, CL = 15 pF; VCC = 3.3 ± 0.3 V 6
Propagation delay time tPLH,tPHL 0.5 2.2 4.1 ns Ta = 25 °C; RL = 1 MΩ, CL = 15 pF; VCC = 5.0 ± 0.5 V 6
Propagation delay time tPLH,tPHL 1.5 3.3 5.2 ns Ta = 25 °C; RL = 500 Ω, CL = 50 pF; VCC = 3.3 ± 0.3 V 6
Propagation delay time tPLH,tPHL 0.8 2.74 4.5 ns Ta = 25 °C; RL = 500 Ω, CL = 50 pF; VCC = 5.0 ± 0.5 V 6
Propagation delay time tPLH,tPHL 2 10.5 ns Ta = -40 to 85 °C; RL = 1 MΩ, CL = 15 pF; VCC = 1.8 ± 0.15 V 6
Propagation delay time tPLH,tPHL 0.8 7.5 ns Ta = -40 to 85 °C; RL = 1 MΩ, CL = 15 pF; VCC = 2.5 ± 0.2 V 6
Propagation delay time tPLH,tPHL 0.5 5 ns Ta = -40 to 85 °C; RL = 1 MΩ, CL = 15 pF; VCC = 3.3 ± 0.3 V 6
Propagation delay time tPLH,tPHL 0.5 4.4 ns Ta = -40 to 85 °C; RL = 1 MΩ, CL = 15 pF; VCC = 5.0 ± 0.5 V 6
Propagation delay time tPLH,tPHL 1.5 5.5 ns Ta = -40 to 85 °C; RL = 500 Ω, CL = 50 pF; VCC = 3.3 ± 0.3 V 6
Propagation delay time tPLH,tPHL 0.8 4.8 ns Ta = -40 to 85 °C; RL = 500 Ω, CL = 50 pF; VCC = 5.0 ± 0.5 V 6

CAD (KiCad official)

  • Symbol: TC7SZ08FU
  • Footprint: Package_TO_SOT_SMD:SOT-353_SC-70-5
  • 3D model: SOT-353 (KiCad packages3D, STEP)
  • 3D model files: tc7sz08fu-etched.step / tc7sz08fu-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tc7sz08fu.step / tc7sz08fu.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA(东芝) datasheet (8 pp, sha256 56ab388793957586, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF