component
TC7662BEOA713
Public Made by Adomby adom
Microchip Tech DC-DC Converters, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TC7662BEOA713
Microchip Tech · DC-DC Converters · SOIC-8
TC7662BEOA713 from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOST | input | Connecting this pin to V+ raises the oscillator frequency from the nominal 10 kHz to about 35 kHz, while leaving it open or at GND keeps the nominal frequency. |
| 2 | CAP+ | passive | Positive terminal of pump capacitor C1; when polarized capacitors are used in the inverting mode, the + terminal of C1 must be connected to this pin. |
| 3 | GND | power_in | Ground reference for the device; the LV pin is tied to this node for supply voltages below 3.5 V, and the negative terminal of C2 must be connected here when polarized capacitors are used in the inverting mode. |
| 4 | CAP- | passive | Negative terminal of pump capacitor C1, which the device shifts negatively by V+ volts during the second half of each cycle. |
| 5 | VOUT | power_out | Negative output, VOUT = -VIN for the standard inverting connection; the output must not be shorted to V+ for extended periods when the supply exceeds 5.5 V (transient and start-up conditions are allowed). |
| 6 | LV | input | Low-voltage pin that must be connected to GND for supply voltages below 3.5 V to disable the internal regulator, and must be left open for supplies above 3.5 V; current into LV is limited to 20 µA when V+ is above 3.5 V. |
| 7 | OSC | passive | Oscillator timing node where an external capacitor to ground (with pin 1 open) lowers the oscillator frequency below 10 kHz, with the pump and reservoir capacitors scaled up by the same factor. |
| 8 | V+ | power_in | Positive supply input, specified at 3.0 V to 15 V with LV open or 1.5 V to 3.5 V with LV tied to GND, with an absolute maximum of 16.5 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Current (Boost pin open or GND) | I+ | 80 | 160 | µA | RL = ∞, +25°C | 2 | |
| Supply Current (Boost pin open or GND) | I+ | 180 | µA | , 40°C ≤ TA ≤ +85°C | 2 | ||
| Supply Current (Boost pin = V+) | I+ | 350 | µA | , 40°C ≤ TA ≤ +85°C | 2 | ||
| Supply Voltage Range, High | V+H | 3 | 15 | V | RL = 10 kΩ, LV Open, TMIN ≤ TA ≤ TMAX | 2 | |
| Supply Voltage Range, Low | V+L | 1.5 | 3.5 | V | RL = 10 kΩ, LV to GND, TMIN ≤ TA ≤ TMAX | 2 | |
| Output Source Resistance | ROUT | 120 | Ω | IOUT = 20mA,, 40°C ≤ TA ≤ +85°C | 2 | ||
| Output Source Resistance | ROUT | 300 | Ω | IOUT = 3mA, V+ = 2V, LV to GND,, 40°C ≤ TA ≤ +85°C | 2 | ||
| Oscillator Frequency | fOSC | 5 | 10 | kHz | COSC = 0, Pin 1 Open or GND | 2 | |
| Power Efficiency | PEff | 96 | 96 | % | RL = 5kΩ | 2 | |
| Power Efficiency | PEff | 95 | 97 | % | TMIN ≤ TA ≤ TMAX | 2 | |
| Voltage Conversion Efficiency | VOUTEff | 99 | 99.9 | % | RL = ∞ | 2 | |
| Supply Voltage | 16.5 | V | 2 | ||||
| LV, Boost and OSC Inputs Voltage | -0.3 | V | V+ < 5.5V; maximum printed as (V+ + 0.3V) | 2 | |||
| Current Into LV | 20 | µA | V+ > 3.5V | 2 | |||
| Operating Temperature Range (E suffix) | -40 | 85 | °C | E Suffix | 2 | ||
| Storage Temperature Range | -65 | 150 | °C | 2 | |||
| Lead Temperature (Soldering) | 300 | °C | 10 sec | 2 |
CAD (KiCad official)
- Symbol:
TC7662BEOA713 - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tc7662beoa713-etched.step/tc7662beoa713-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc7662beoa713.step/tc7662beoa713.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (11 pp, sha256
170b231f7f950a57, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TC7662BEOA713
**Microchip Tech** · DC-DC Converters · SOIC-8
TC7662BEOA713 from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BOOST | input | Connecting this pin to V+ raises the oscillator frequency from the nominal 10 kHz to about 35 kHz, while leaving it open or at GND keeps the nominal frequency. |
| 2 | CAP+ | passive | Positive terminal of pump capacitor C1; when polarized capacitors are used in the inverting mode, the + terminal of C1 must be connected to this pin. |
| 3 | GND | power_in | Ground reference for the device; the LV pin is tied to this node for supply voltages below 3.5 V, and the negative terminal of C2 must be connected here when polarized capacitors are used in the inverting mode. |
| 4 | CAP- | passive | Negative terminal of pump capacitor C1, which the device shifts negatively by V+ volts during the second half of each cycle. |
| 5 | VOUT | power_out | Negative output, VOUT = -VIN for the standard inverting connection; the output must not be shorted to V+ for extended periods when the supply exceeds 5.5 V (transient and start-up conditions are allowed). |
| 6 | LV | input | Low-voltage pin that must be connected to GND for supply voltages below 3.5 V to disable the internal regulator, and must be left open for supplies above 3.5 V; current into LV is limited to 20 µA when V+ is above 3.5 V. |
| 7 | OSC | passive | Oscillator timing node where an external capacitor to ground (with pin 1 open) lowers the oscillator frequency below 10 kHz, with the pump and reservoir capacitors scaled up by the same factor. |
| 8 | V+ | power_in | Positive supply input, specified at 3.0 V to 15 V with LV open or 1.5 V to 3.5 V with LV tied to GND, with an absolute maximum of 16.5 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Current (Boost pin open or GND) | I+ | | 80 | 160 | µA | RL = ∞, +25°C | 2 |
| Supply Current (Boost pin open or GND) | I+ | | | 180 | µA |, 40°C ≤ TA ≤ +85°C | 2 |
| Supply Current (Boost pin = V+) | I+ | | | 350 | µA |, 40°C ≤ TA ≤ +85°C | 2 |
| Supply Voltage Range, High | V+H | 3 | | 15 | V | RL = 10 kΩ, LV Open, TMIN ≤ TA ≤ TMAX | 2 |
| Supply Voltage Range, Low | V+L | 1.5 | | 3.5 | V | RL = 10 kΩ, LV to GND, TMIN ≤ TA ≤ TMAX | 2 |
| Output Source Resistance | ROUT | | | 120 | Ω | IOUT = 20mA,, 40°C ≤ TA ≤ +85°C | 2 |
| Output Source Resistance | ROUT | | | 300 | Ω | IOUT = 3mA, V+ = 2V, LV to GND,, 40°C ≤ TA ≤ +85°C | 2 |
| Oscillator Frequency | fOSC | 5 | 10 | | kHz | COSC = 0, Pin 1 Open or GND | 2 |
| Power Efficiency | PEff | 96 | 96 | | % | RL = 5kΩ | 2 |
| Power Efficiency | PEff | 95 | 97 | | % | TMIN ≤ TA ≤ TMAX | 2 |
| Voltage Conversion Efficiency | VOUTEff | 99 | 99.9 | | % | RL = ∞ | 2 |
| Supply Voltage | | | | 16.5 | V | | 2 |
| LV, Boost and OSC Inputs Voltage | | -0.3 | | | V | V+ < 5.5V; maximum printed as (V+ + 0.3V) | 2 |
| Current Into LV | | | | 20 | µA | V+ > 3.5V | 2 |
| Operating Temperature Range (E suffix) | | -40 | | 85 | °C | E Suffix | 2 |
| Storage Temperature Range | | -65 | | 150 | °C | | 2 |
| Lead Temperature (Soldering) | | | | 300 | °C | 10 sec | 2 |
## CAD (KiCad official)
- Symbol: `TC7662BEOA713`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tc7662beoa713-etched.step` / `tc7662beoa713-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tc7662beoa713.step` / `tc7662beoa713.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589799052922953728) (11 pp, sha256 `170b231f7f950a57`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tc7662beoa713-datasheet.pdf)