# TC7650CPD

**Microchip Tech** · Operational Amplifier · PDIP-14

TC7650CPD from Microchip Tech, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CB | passive | Nulling capacitor pin for CB (0.1µF for the internal clock), with the other side returned to CRETN (pin 8). |
| 2 | CA | passive | Nulling capacitor pin for CA (0.1µF for the internal clock), with the other side returned to CRETN (pin 8). |
| 3 | NC | unconnected | No internal connection; left unused to ease input guarding. |
| 4 | -INPUT | input | Inverting input of the chopper-stabilized amplifier, with high-impedance CMOS input (typ 10^12 Ω). |
| 5 | +INPUT | input | Non-inverting input of the chopper-stabilized amplifier, with high-impedance CMOS input (typ 10^12 Ω). |
| 6 | NC | unconnected | No internal connection; left unused to ease input guarding. |
| 7 | VSS | power_in | Negative power supply; total supply VDD to VSS is 4.5V to 16V operating, +18V absolute maximum, and INT/EXT is tied here to use an external clock. |
| 8 | CRETN | passive | Capacitor current return pin, the common connection for the CA and CB nulling capacitors, routed by a separate trace. |
| 9 | OUTPUT CLAMP | passive | Output voltage clamp connection to the feedback network to reduce overload recovery time; impedance across the clamp should be greater than 100kΩ for full effect. |
| 10 | OUTPUT | output | Amplifier output, a high-impedance stage (about 18kΩ) with output short circuit duration indefinite. |
| 11 | VDD | power_in | Positive power supply; total supply VDD to VSS is 4.5V to 16V operating, +18V absolute maximum. |
| 12 | INT CLK OUT | output | Internal clock output providing the 200Hz nominal chopping frequency. |
| 13 | EXT CLK IN | input | External clock input, which carries a 400Hz nominal signal when INT/EXT is high or open and swings between VDD and ground for supplies up to ±6V. |
| 14 | INT/EXT | input | Selects internal or external clock; has an internal pull-up and may be left open for internal clock, and is tied to VSS for external clock. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-14 |
| Category | Amplifiers |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage | VOS |  | 0.7 | 5 | µV | TA = +25°C | 3 |
| Input Offset Voltage Average Temperature Coefficient | ΔVOS/ΔT |  | 0.01 | 0.05 | µV/°C | Operating Temperature Range | 3 |
| Input Bias Current | IBIAS |  | 1.5 | 10 | pA | TA = +25°C | 3 |
| Input Bias Current | IBIAS |  | 35 | 150 | pA | 0°C ≤ TA ≤ +70°C | 3 |
| Common Mode Voltage Range | CMVR | -5 |  | 1.6 | V |  | 3 |
| Common Mode Rejection Ratio | CMRR | 120 | 130 |  | dB | CMVR = -5V to +1.5V | 3 |
| Large Signal Voltage Gain | A | 120 | 130 |  | dB | RL = 10k | 3 |
| Output Voltage Swing | VOUT | -4.7 | 4.85 | 4.7 | V | RL = 10k | 3 |
| Clamp ON Current |  | 25 | 70 | 200 | µA | RL = 100k (Note 1) | 3 |
| Internal Chopping Frequency | fCH | 120 | 200 | 375 | Hz | Pins 12-14 Open (DIP) | 3 |
| Operating Supply Range | VDD, VSS | 4.5 |  | 16 | V |  | 3 |
| Supply Current | IS |  | 2 | 3.5 | mA | No Load | 3 |
| Power Supply Rejection Ratio | PSRR | 120 | 130 |  | dB | VS = ±3V to ±8V | 3 |
| Input Noise Voltage | eNP-P |  | 2 |  | µVP-P | RS = 100, 0 to 10Hz | 3 |
| Unity Gain Bandwidth | BW |  | 2 |  | MHz | Unity Gain (+1) | 3 |
| Slew Rate | SR |  | 2.5 |  | V/µs | CL = 50pF, RL = 10k | 3 |
| Total Supply Voltage (VDD to VSS) |  |  |  | 18 | V |  | 3 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 3 |
| Current Into Any Pin |  |  |  | 10 | mA |  | 3 |
| Current Into Any Pin While Operating |  |  |  | 100 | µA | While Operating (Note 3) | 3 |
| Operating Temperature Range C Device |  | 0 |  | 70 | °C |  | 3 |

## CAD (KiCad official)

- Symbol: `TC7650CPD`
- Footprint: `Package_DIP:DIP-14_W7.62mm`
- 3D model: PDIP-14 (KiCad packages3D, STEP)
- 3D model files: `tc7650cpd-etched.step` / `tc7650cpd-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tc7650cpd.step` / `tc7650cpd.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/tc7650cpd-datasheet.pdf) (14 pp, sha256 `d0de65d4c7812942`, retrieved 2026-10-31, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tc7650cpd-datasheet.pdf)