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TC74LCX541F

Public Made by Adom

by adom

TOSHIBA Buffers, Drivers, Receivers, Transceivers, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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TC74LCX541F

TOSHIBA · Buffers, Drivers, Receivers, Transceivers · SOP-20

TC74LCX541F from TOSHIBA, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low output enable 1; when OE1 is high the outputs go to high impedance (truth table: OE1 or OE2 high gives Z).
2 A1 input Data input 1 of the non-inverting 3-state buffer; input operating range is 0 to 5.5 V, so it tolerates 5 V signals.
3 A2 input Data input 2 of the non-inverting 3-state buffer; input operating range is 0 to 5.5 V, so it tolerates 5 V signals.
4 A3 input Data input 3 of the non-inverting 3-state buffer; input operating range is 0 to 5.5 V, so it tolerates 5 V signals.
5 A4 input Data input 4 of the non-inverting 3-state buffer; input operating range is 0 to 5.5 V, so it tolerates 5 V signals.
6 A5 input Data input 5 of the non-inverting 3-state buffer; input operating range is 0 to 5.5 V, so it tolerates 5 V signals.
7 A6 input Data input 6 of the non-inverting 3-state buffer; input operating range is 0 to 5.5 V, so it tolerates 5 V signals.
8 A7 input Data input 7 of the non-inverting 3-state buffer; input operating range is 0 to 5.5 V, so it tolerates 5 V signals.
9 A8 input Data input 8 of the non-inverting 3-state buffer; input operating range is 0 to 5.5 V, so it tolerates 5 V signals.
10 GND power_in Ground reference for the device.
11 Y8 tri_state Buffered 3-state output 8; high impedance when either output enable is high, drives 24 mA min at VCC 3.0 V.
12 Y7 tri_state Buffered 3-state output 7; high impedance when either output enable is high, drives 24 mA min at VCC 3.0 V.
13 Y6 tri_state Buffered 3-state output 6; high impedance when either output enable is high, drives 24 mA min at VCC 3.0 V.
14 Y5 tri_state Buffered 3-state output 5; high impedance when either output enable is high, drives 24 mA min at VCC 3.0 V.
15 Y4 tri_state Buffered 3-state output 4; high impedance when either output enable is high, drives 24 mA min at VCC 3.0 V.
16 Y3 tri_state Buffered 3-state output 3; high impedance when either output enable is high, drives 24 mA min at VCC 3.0 V.
17 Y2 tri_state Buffered 3-state output 2; high impedance when either output enable is high, drives 24 mA min at VCC 3.0 V.
18 Y1 tri_state Buffered 3-state output 1; high impedance when either output enable is high, drives 24 mA min at VCC 3.0 V.
19 OE2 input Active-low output enable 2; when OE2 is high the outputs go to high impedance (truth table: OE1 or OE2 high gives Z).
20 VCC power_in Positive supply; operating range 1.65 to 3.6 V, absolute maximum 7.0 V.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package SOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Power supply voltage VCC -0.5 7 V 3
DC input voltage VIN -0.5 7 V 3
DC output voltage VOUT -0.5 7 V Note 2: Output in OFF state 3
DC output voltage VOUT -0.5 V Note 3: High or low state 3
Input diode current IIK 50 mA 3
Output diode current IOK 50 mA Note 4 3
DC output current IOUT 50 mA 3
Power dissipation PD 180 mW 3
DC VCC/ground current ICC/IGND 100 mA 3
Storage temperature Tstg -65 150 °C 3
Power supply voltage VCC 1.65 3.6 V 3
Power supply voltage (data retention) VCC 1.5 3.6 V Note 2: Data retention only 3
Input voltage VIN 0 5.5 V 3
Output voltage VOUT 0 5.5 V Note 3: Output in OFF state 3
Output voltage VOUT 0 V Note 4: High or low state 3
Output current IOH/IOL 24 mA VCC 3.0 to 3.6 V (Note 5) 3
Output current IOH/IOL 12 mA VCC 2.7 to 3.0 V (Note 6) 3
Operating temperature Topr -40 85 °C 3
Input rise and fall time dt/dv 0 10 ns/V VIN 0.8 to 2.0 V, VCC 3.0 V (Note 7) 3
H-level input voltage VIH 1.7 V VCC 2.3 to 2.7 V 4
H-level input voltage VIH 2 V VCC 2.7 to 3.6 V 4
L-level input voltage VIL 0.7 V VCC 2.3 to 2.7 V 4
L-level input voltage VIL 0.8 V VCC 2.7 to 3.6 V 4
H-level output voltage VOH 1.05 V VIN = VIH or VIL, IOH = 4 mA, VCC 1.65 V 4
H-level output voltage VOH 1.7 V VIN = VIH or VIL, IOH = 8 mA, VCC 2.3 V 4
H-level output voltage VOH 2.2 V VIN = VIH or VIL, IOH = 12 mA, VCC 2.7 V 4
H-level output voltage VOH 2.4 V VIN = VIH or VIL, IOH = 18 mA, VCC 3.0 V 4
L-level output voltage VOL 0.2 V VIN = VIH or VIL, IOL = 100 µA, VCC 1.65 to 3.6 V 4
L-level output voltage VOL 0.45 V VIN = VIH or VIL, IOL = 4 mA, VCC 1.65 V 4
L-level output voltage VOL 0.7 V VIN = VIH or VIL, IOL = 8 mA, VCC 2.3 V 4
L-level output voltage VOL 0.4 V VIN = VIH or VIL, IOL = 12 mA, VCC 2.7 V 4
L-level output voltage VOL 0.55 V VIN = VIH or VIL, IOL = 24 mA, VCC 3.0 V 4
Input leakage current IIN 5 µA VIN 0 to 5.5 V, VCC 1.65 to 3.6 V 4
3-state output off-state current IOZ 5 µA VIN = VIH or VIL, VOUT 0 to 5.5 V, VCC 1.65 to 3.6 V 4
Power off leakage current IOFF 10 µA VIN/VOUT 5.5 V, VCC 0 4
Quiescent supply current ICC 10 µA VIN = VCC or GND, VCC 1.65 to 3.6 V 4
Increase in ICC per input ICC 500 µA VIH = VCC − 0.6 V (per 1 input), VCC 2.7 to 3.6 V 4
Propagation delay time tpLH/tpHL 25 ns VCC 1.8±0.15 V; Figure 1, Figure 2 5
Propagation delay time tpLH/tpHL 8.5 ns VCC 2.5±0.2 V; Figure 1, Figure 2 5
Propagation delay time tpLH/tpHL 7.5 ns VCC 2.7 V; Figure 1, Figure 2 5
Propagation delay time tpLH/tpHL 1.5 6.5 ns VCC 3.3±0.3 V; Figure 1, Figure 2 5
Output enable time tpZL/tpZH 34 ns VCC 1.8±0.15 V; Figure 1, Figure 3 5
Output enable time tpZL/tpZH 17 ns VCC 2.5±0.2 V; Figure 1, Figure 3 5
Output enable time tpZL/tpZH 9.5 ns VCC 2.7 V; Figure 1, Figure 3 5
Output enable time tpZL/tpZH 1.5 8.5 ns VCC 3.3±0.3 V; Figure 1, Figure 3 5
Output disable time tpLZ/tpHZ 32 ns VCC 1.8±0.15 V; Figure 1, Figure 3 5
Output disable time tpLZ/tpHZ 16 ns VCC 2.5±0.2 V; Figure 1, Figure 3 5
Output disable time tpLZ/tpHZ 8.5 ns VCC 2.7 V; Figure 1, Figure 3 5
Output disable time tpLZ/tpHZ 1.5 7.5 ns VCC 3.3±0.3 V; Figure 1, Figure 3 5
Output to output skew tosLH/tosHL 1 ns VCC 3.3±0.3 V; Note: parameter guaranteed by design 5

CAD (KiCad official)

  • Symbol: TC74LCX541F
  • Footprint: Package_SO:SOP-20_7.5x12.8mm_P1.27mm
  • 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: tc74lcx541f-etched.step / tc74lcx541f-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tc74lcx541f.step / tc74lcx541f.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (10 pp, sha256 4c14b8c1c8aa52ed, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF