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TC74HC74AF

Public Made by Adom

by adom

TOSHIBA(东芝) Flip Flops, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TC74HC74AF

TOSHIBA(东芝) · Flip Flops · SOP-14

TC74HC74AF from TOSHIBA(东芝), in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1CLR input Active-low asynchronous clear input of flip-flop 1, independent of the clock; an L level sets Q low.
2 1D input Data input of flip-flop 1, transferred to Q on the positive-going clock transition.
3 1CK input Clock input of flip-flop 1, triggered on the positive-going transition.
4 1PR input Active-low asynchronous preset input of flip-flop 1, independent of the clock; an L level sets Q high.
5 1Q output True output of flip-flop 1 with drive of
6 1Q̄ output Complementary output of flip-flop 1 with drive of
7 GND power_in Ground pin (0 V).
8 2Q̄ output Complementary output of flip-flop 2 with drive of
9 2Q output True output of flip-flop 2 with drive of
10 2PR input Active-low asynchronous preset input of flip-flop 2, independent of the clock; an L level sets Q high.
11 2CK input Clock input of flip-flop 2, triggered on the positive-going transition.
12 2D input Data input of flip-flop 2, transferred to Q on the positive-going clock transition.
13 2CLR input Active-low asynchronous clear input of flip-flop 2, independent of the clock; an L level sets Q low.
14 VCC power_in Supply voltage pin, operating range 2 to 6 V (absolute maximum -0.5 to 7 V).

Key specifications

Parameter Value
Manufacturer TOSHIBA(东芝)
Package SOP-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 3
DC input voltage VIN -0.5 V upper limit printed as VCC + 0.5 3
DC output voltage VOUT -0.5 V upper limit printed as VCC + 0.5 3
Input diode current IIK -20 20 mA 3
Output diode current IOK -20 20 mA 3
DC output current IOUT -25 25 mA 3
DC VCC/ground current ICC -50 50 mA 3
Power dissipation PD 180 mW SOP package 3
Storage temperature Tstg -65 150 °C 3
Supply voltage VCC 2 6 V 3
Input voltage VIN 0 V upper limit printed as VCC 3
Output voltage VOUT 0 V upper limit printed as VCC 3
Operating temperature Topr -40 85 °C 3
Input rise and fall time tr, tf 0 1000 ns VCC = 2.0 V 3
Input rise and fall time tr, tf 0 500 ns VCC = 4.5 V 3
Input rise and fall time tr, tf 0 400 ns VCC = 6.0 V 3
High-level input voltage VIH 1.5 V VCC = 2.0 V; Ta = -40 to 85°C 4
High-level input voltage VIH 3.15 V VCC = 4.5 V; Ta = -40 to 85°C 4
High-level input voltage VIH 4.2 V VCC = 6.0 V; Ta = -40 to 85°C 4
Low-level input voltage VIL 0.5 V VCC = 2.0 V; Ta = -40 to 85°C 4
Low-level input voltage VIL 1.35 V VCC = 4.5 V; Ta = -40 to 85°C 4
Low-level input voltage VIL 1.8 V VCC = 6.0 V; Ta = -40 to 85°C 4
High-level output voltage VOH 1.9 V VCC = 2.0 V; IOH = -20 μA; VIN = VIH or VIL; Ta = -40 to 85°C 4
High-level output voltage VOH 4.4 V VCC = 4.5 V; IOH = -20 μA; VIN = VIH or VIL; Ta = -40 to 85°C 4
High-level output voltage VOH 5.9 V VCC = 6.0 V; IOH = -20 μA; VIN = VIH or VIL; Ta = -40 to 85°C 4
High-level output voltage VOH 4.13 V VCC = 4.5 V; IOH = -4 mA; VIN = VIH or VIL; Ta = -40 to 85°C 4
High-level output voltage VOH 5.63 V VCC = 6.0 V; IOH = -5.2 mA; VIN = VIH or VIL; Ta = -40 to 85°C 4
Low-level output voltage VOL 0.1 V VCC = 2.0 V; IOL = 20 μA; VIN = VIH or VIL; Ta = -40 to 85°C 4
Low-level output voltage VOL 0.33 V VCC = 4.5 V; IOL = 4 mA; VIN = VIH or VIL; Ta = -40 to 85°C 4
Input leakage current IIN -1 1 μA VCC = 6.0 V; VIN = VCC or GND; Ta = -40 to 85°C 4
Quiescent supply current ICC 20 μA VCC = 6.0 V; VIN = VCC or GND; Ta = -40 to 85°C 4
Minimum pulse width (CK) low tW(L) 95 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum pulse width (CK) low tW(L) 19 ns VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum pulse width (CK) low tW(L) 16 ns VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum pulse width (CK) high tW(H) 95 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum pulse width (CK) high tW(H) 19 ns VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum pulse width (CK) high tW(H) 16 ns VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum pulse width (CLR, PR) low tW(L) 95 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum pulse width (CLR, PR) low tW(L) 19 ns VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum pulse width (CLR, PR) low tW(L) 16 ns VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum set-up time ts 95 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum set-up time ts 19 ns VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum set-up time ts 16 ns VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum hold time th 0 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum removal time (CLR, PR) trem 30 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum removal time (CLR, PR) trem 6 ns VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Minimum removal time (CLR, PR) trem 5 ns VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Clock frequency f 5 MHz VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Clock frequency f 25 MHz VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Clock frequency f 29 MHz VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 5
Propagation delay time (CK-Q, Q̄) tpLH, tpHL 190 ns VCC = 2.0 V; CL = 50 pF; Ta = -40 to 85°C; input tr = tf = 6 ns 6
Propagation delay time (CK-Q, Q̄) tpLH, tpHL 38 ns VCC = 4.5 V; CL = 50 pF; Ta = -40 to 85°C; input tr = tf = 6 ns 6
Propagation delay time (CK-Q, Q̄) tpLH, tpHL 32 ns VCC = 6.0 V; CL = 50 pF; Ta = -40 to 85°C; input tr = tf = 6 ns 6

CAD (KiCad official)

  • Symbol: TC74HC74AF
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: tc74hc74af-etched.step / tc74hc74af-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tc74hc74af.step / tc74hc74af.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA(东芝) datasheet (9 pp, sha256 f0406359206fc18a, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF