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TC74HC4538AF

Public Made by Adom

by adom

TOSHIBA Monostable Multivibrators, SOP-16. Pinout reviewed by a person against the datasheet, KiCad symbol/footprint/3D.

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TC74HC4538AF

TOSHIBA · Monostable Multivibrators · SOP-16

TC74HC4538AF from TOSHIBA, in a SOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 1T1 input Trigger input 1 for channel 1 monostable circuit; connects to external timing network (CX, RX) for output pulse duration control.
2 1T2 input Trigger input 2 for channel 1 monostable circuit; connects to external timing network (CX, RX) for output pulse duration control.
3 1CD input Clear/discharge input for channel 1; low level asynchronously resets Q output to low and forces IC to stand-by state.
4 B1 input Negative-edge trigger input for channel 1; output triggered on B1 falling edge when 1A input is low, Schmitt trigger type with tr/tf ≤ 1 μs.
5 1A input Positive-edge trigger input for channel 1; output triggered on 1A rising edge when B1 input is high, Schmitt trigger type with tr/tf ≤ 1 μs.
6 1Q output Q output for channel 1; pulses high during monostable period with duration twOUT = 0.70·CX·RX, 4 mA min output drive capability.
7 Q1 output Q̄ (inverted) output for channel 1; complementary to 1Q, pulses low during monostable period, 4 mA min output drive capability.
8 GND power_in Ground; negative supply rail and return reference (0 V).
9 2A input Positive-edge trigger input for channel 2; output triggered on 2A rising edge when B2 input is high, Schmitt trigger type with tr/tf ≤ 1 μs.
10 Q2 output Q̄ (inverted) output for channel 2; complementary to 2Q, pulses low during monostable period, 4 mA min output drive capability.
11 2CD input Clear/discharge input for channel 2; low level asynchronously resets Q output to low and forces IC to stand-by state.
12 B2 input Negative-edge trigger input for channel 2; output triggered on B2 falling edge when 2A input is low, Schmitt trigger type with tr/tf ≤ 1 μs.
13 2T2 input Trigger input 2 for channel 2 monostable circuit; connects to external timing network (CX, RX) for output pulse duration control.
14 2T1 input Trigger input 1 for channel 2 monostable circuit; connects to external timing network (CX, RX) for output pulse duration control.
15 2Q output Q output for channel 2; pulses high during monostable period with duration twOUT = 0.70·CX·RX, 4 mA min output drive capability.
16 VCC power_in Supply voltage positive rail; operating range 2 V to 6 V, 4.5 V to 6 V recommended for optimum noise immunity.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package SOP-16
Category Logic
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC -0.5 7 V 6
DC input voltage VIN -0.5 V Printed as -0.5 to VCC + 0.5 6
DC output voltage VOUT -0.5 V Printed as -0.5 to VCC + 0.5 6
Input diode current IIK -20 20 mA 6
Output diode current IOK -20 20 mA 6
DC output current IOUT -25 25 mA 6
DC VCC/ground current ICC -50 50 mA 6
Power dissipation PD 180 mW SOP/TSSOP package (DIP: 500 mW, Note 1) 6
Storage temperature Tstg -65 150 °C 6
Supply voltage VCC 2 6 V 6
Input voltage VIN 0 V Printed as 0 to VCC 6
Output voltage VOUT 0 V Printed as 0 to VCC 6
Operating temperature Topr -40 85 °C 6
Input rise and fall time (CD only) tr, tf 0 1000 ns VCC = 2.0 V 6
Input rise and fall time (CD only) tr, tf 0 500 ns VCC = 4.5 V 6
Input rise and fall time (CD only) tr, tf 0 400 ns VCC = 6.5 V (as printed) 6
External resistor RX 5 kΩ VCC = 2.0 V (Note 1) 6
External resistor RX 1 kΩ VCC ≥ 3.0 V (Note 1) 6
High-level input voltage VIH 1.5 V VCC = 2.0 V; Ta = -40 to 85°C 7
High-level input voltage VIH 3.15 V VCC = 4.5 V; Ta = -40 to 85°C 7
High-level input voltage VIH 4.2 V VCC = 6.0 V; Ta = -40 to 85°C 7
Low-level input voltage VIL 0.5 V VCC = 2.0 V; Ta = -40 to 85°C 7
Low-level input voltage VIL 1.35 V VCC = 4.5 V; Ta = -40 to 85°C 7
Low-level input voltage VIL 1.8 V VCC = 6.0 V; Ta = -40 to 85°C 7
High-level output voltage (Q, Q̄) VOH 1.9 V VIN = VIH or VIL; IOH = -20 μA; VCC = 2.0 V; Ta = -40 to 85°C 7
High-level output voltage (Q, Q̄) VOH 4.4 V VIN = VIH or VIL; IOH = -20 μA; VCC = 4.5 V; Ta = -40 to 85°C 7
High-level output voltage (Q, Q̄) VOH 5.9 V VIN = VIH or VIL; IOH = -20 μA; VCC = 6.0 V; Ta = -40 to 85°C 7
High-level output voltage (Q, Q̄) VOH 4.13 V VIN = VIH or VIL; IOH = -4 mA; VCC = 4.5 V; Ta = -40 to 85°C 7
High-level output voltage (Q, Q̄) VOH 5.63 V VIN = VIH or VIL; IOH = -5.2 mA; VCC = 6.0 V; Ta = -40 to 85°C 7
Low-level output voltage (Q, Q̄) VOL 0.1 V VIN = VIH or VIL; IOL = 20 μA; VCC = 2.0 V; Ta = -40 to 85°C 7
Low-level output voltage (Q, Q̄) VOL 0.33 V VIN = VIH or VIL; IOL = 4 mA; VCC = 4.5 V; Ta = -40 to 85°C 7
Input leakage current IIN -1 1 μA VIN = VCC or GND; VCC = 6.0 V; Ta = -40 to 85°C 7
T2 terminal input leakage current IIN -5 5 μA VIN = VCC or GND; VCC = 6.0 V; Ta = -40 to 85°C 7
Quiescent supply current ICC 40 μA VIN = VCC or GND; VCC = 6.0 V; Ta = -40 to 85°C 7
Active-state supply current (per circuit) ICC' 160 μA VIN = VCC or GND; RX/CX = 0.5 VCC; VCC = 2.0 V; Ta = -40 to 85°C 7
Active-state supply current (per circuit) ICC' 400 μA VIN = VCC or GND; RX/CX = 0.5 VCC; VCC = 4.5 V; Ta = -40 to 85°C 7
Active-state supply current (per circuit) ICC' 800 μA VIN = VCC or GND; RX/CX = 0.5 VCC; VCC = 6.0 V; Ta = -40 to 85°C 7
Minimum pulse width (A, B) tw(L), tw(H) 95 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 8
Minimum pulse width (A, B) tw(L), tw(H) 19 ns VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 8
Minimum pulse width (A, B) tw(L), tw(H) 16 ns VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 8
Minimum clear width (CD) tw(L) 95 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 8
Minimum clear width (CD) tw(L) 19 ns VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 8
Minimum clear width (CD) tw(L) 16 ns VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 8
Minimum clear removal time trem 15 ns VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 8
Minimum clear removal time trem 5 ns VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 8
Propagation delay time (A, B → Q, Q̄) tpLH, tpHL 315 ns CL = 50 pF; VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 9
Propagation delay time (A, B → Q, Q̄) tpLH, tpHL 63 ns CL = 50 pF; VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 9
Propagation delay time (A, B → Q, Q̄) tpLH, tpHL 54 ns CL = 50 pF; VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 9
Propagation delay time (CD → Q, Q̄) tpLH, tpHL 245 ns CL = 50 pF; VCC = 2.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 9
Propagation delay time (CD → Q, Q̄) tpLH, tpHL 49 ns CL = 50 pF; VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns 9
Propagation delay time (CD → Q, Q̄) tpLH, tpHL 42 ns CL = 50 pF; VCC = 6.0 V; Ta = -40 to 85°C; input tr = tf = 6 ns 9
Output pulse width twOUT 70 96 μs CX = 0.01 μF; RX = 10 kΩ; VCC = 2.0 V; Ta = -40 to 85°C 9
Output pulse width twOUT 69 85 μs CX = 0.01 μF; RX = 10 kΩ; VCC = 4.5 V; Ta = -40 to 85°C 9
Input capacitance CIN 10 pF Ta = -40 to 85°C 9
Output pulse width error between circuits (in same package) ΔtwOUT -1 1 % Ta = 25°C 9

CAD (KiCad official)

  • Symbol: TC74HC4538AF
  • Footprint: Package_SO:SOIC-16_3.9x9.9mm_P1.27mm
  • 3D model: SOP-16 (KiCad packages3D, STEP)
  • 3D model files: tc74hc4538af-etched.step / tc74hc4538af-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tc74hc4538af.step / tc74hc4538af.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (14 pp, sha256 a45087ec6b1bcbd9, retrieved 2026-10-21, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF