component
TC74HC273AF
Public Made by Adomby adom
TOSHIBA Flip Flops, SOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownTC74HC273AF
TOSHIBA · Flip Flops · SOP-20
TC74HC273AF from TOSHIBA, in a SOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CLR | input | Active-low asynchronous clear input; when held L the Q outputs are forced low independent of other inputs. |
| 2 | Q1 | output | Flip-flop 1 output, drives 10 LSTTL loads ( |
| 3 | D1 | input | Flip-flop 1 data input, transferred to Q1 on the rising clock edge. |
| 4 | D2 | input | Flip-flop 2 data input, transferred to Q2 on the rising clock edge. |
| 5 | Q2 | output | Flip-flop 2 output, drives 10 LSTTL loads ( |
| 6 | Q3 | output | Flip-flop 3 output, drives 10 LSTTL loads ( |
| 7 | D3 | input | Flip-flop 3 data input, transferred to Q3 on the rising clock edge. |
| 8 | D4 | input | Flip-flop 4 data input, transferred to Q4 on the rising clock edge. |
| 9 | Q4 | output | Flip-flop 4 output, drives 10 LSTTL loads ( |
| 10 | GND | power_in | Ground pin (0 V). |
| 11 | CK | input | Common clock input; data is transferred to the Q outputs on the positive-going edge. |
| 12 | Q5 | output | Flip-flop 5 output, drives 10 LSTTL loads ( |
| 13 | D5 | input | Flip-flop 5 data input, transferred to Q5 on the rising clock edge. |
| 14 | D6 | input | Flip-flop 6 data input, transferred to Q6 on the rising clock edge. |
| 15 | Q6 | output | Flip-flop 6 output, drives 10 LSTTL loads ( |
| 16 | Q7 | output | Flip-flop 7 output, drives 10 LSTTL loads ( |
| 17 | D7 | input | Flip-flop 7 data input, transferred to Q7 on the rising clock edge. |
| 18 | D8 | input | Flip-flop 8 data input, transferred to Q8 on the rising clock edge. |
| 19 | Q8 | output | Flip-flop 8 output, drives 10 LSTTL loads ( |
| 20 | VCC | power_in | Supply voltage, operating range 2 to 6 V (absolute maximum -0.5 to 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-20 |
| Category | Logic |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VCC | 2 | 6 | V | 3 | ||
| Input voltage | VIN | 0 | V | 3 | |||
| Output voltage | VOUT | 0 | V | 3 | |||
| Operating temperature | Topr | -40 | 85 | °C | 3 | ||
| Input rise and fall time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V | 3 | |
| Input rise and fall time | tr, tf | 0 | 500 | ns | VCC = 4.5 V | 3 | |
| Input rise and fall time | tr, tf | 0 | 400 | ns | VCC = 6.0 V | 3 | |
| Supply voltage range | VCC | -0.5 | 7 | V | 3 | ||
| DC input voltage | VIN | -0.5 | V | 3 | |||
| DC output voltage | VOUT | -0.5 | V | 3 | |||
| Input diode current | IIK | -20 | 20 | mA | 3 | ||
| Output diode current | IOK | -20 | 20 | mA | 3 | ||
| DC output current | IOUT | -25 | 25 | mA | 3 | ||
| DC VCC/ground current | ICC | -50 | 50 | mA | 3 | ||
| Power dissipation | PD | 180 | mW | SOP package | 3 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 3 | ||
| High-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; Ta = 25°C | 4 | ||
| High-level input voltage | VIH | 3.15 | V | VCC = 4.5 V; Ta = 25°C | 4 | ||
| High-level input voltage | VIH | 4.2 | V | VCC = 6.0 V; Ta = 25°C | 4 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; Ta = 25°C | 4 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC = 4.5 V; Ta = 25°C | 4 | ||
| Low-level input voltage | VIL | 1.8 | V | VCC = 6.0 V; Ta = 25°C | 4 | ||
| High-level output voltage | VOH | 1.9 | V | IOH = -20 µA; VCC = 2.0 V; Ta = 25°C | 4 | ||
| High-level output voltage | VOH | 4.4 | V | IOH = -20 µA; VCC = 4.5 V; Ta = 25°C | 4 | ||
| High-level output voltage | VOH | 5.9 | V | IOH = -20 µA; VCC = 6.0 V; Ta = 25°C | 4 | ||
| High-level output voltage | VOH | 4.18 | V | IOH = -4 mA; VCC = 4.5 V; Ta = 25°C | 4 | ||
| High-level output voltage | VOH | 4.13 | V | IOH = -4 mA; VCC = 4.5 V; Ta = -40 to 85°C | 4 | ||
| High-level output voltage | VOH | 5.68 | V | IOH = -5.2 mA; VCC = 6.0 V; Ta = 25°C | 4 | ||
| High-level output voltage | VOH | 5.63 | V | IOH = -5.2 mA; VCC = 6.0 V; Ta = -40 to 85°C | 4 | ||
| Low-level output voltage | VOL | 0.1 | V | IOL = 20 µA; VCC = 2.0 V; Ta = 25°C | 4 | ||
| Low-level output voltage | VOL | 0.26 | V | IOL = 4 mA; VCC = 4.5 V; Ta = 25°C | 4 | ||
| Low-level output voltage | VOL | 0.33 | V | IOL = 4 mA; VCC = 4.5 V; Ta = -40 to 85°C | 4 | ||
| Input leakage current | IIN | -0.1 | 0.1 | µA | VIN = VCC or GND; VCC = 6.0 V; Ta = 25°C | 4 | |
| Input leakage current | IIN | -1 | 1 | µA | VIN = VCC or GND; VCC = 6.0 V; Ta = -40 to 85°C | 4 | |
| Quiescent supply current | ICC | 4 | µA | VIN = VCC or GND; VCC = 6.0 V; Ta = 25°C | 4 | ||
| Quiescent supply current | ICC | 40 | µA | VIN = VCC or GND; VCC = 6.0 V; Ta = -40 to 85°C | 4 | ||
| Minimum pulse width (CK) | tW(L) | 15 | ns | VCC = 4.5 V; Ta = 25°C; input tr = tf = 6 ns | 4 | ||
| Minimum pulse width (CK) | tW(L) | 19 | ns | VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns | 4 | ||
| Minimum set-up time | ts | 15 | ns | VCC = 4.5 V; Ta = 25°C; input tr = tf = 6 ns | 4 | ||
| Minimum set-up time | ts | 19 | ns | VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns | 4 | ||
| Clock frequency | f | 30 | MHz | VCC = 4.5 V; Ta = 25°C; input tr = tf = 6 ns | 4 | ||
| Clock frequency | f | 24 | MHz | VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns | 4 | ||
| Propagation delay time (CK-Q) | tpLH, tpHL | 29 | ns | CL = 50 pF; VCC = 4.5 V; Ta = 25°C; input tr = tf = 6 ns | 5 | ||
| Propagation delay time (CK-Q) | tpLH, tpHL | 36 | ns | CL = 50 pF; VCC = 4.5 V; Ta = -40 to 85°C; input tr = tf = 6 ns | 5 |
CAD (KiCad official)
- Symbol:
TC74HC273AF - Footprint:
Package_SO:SOP-20_7.5x12.8mm_P1.27mm - 3D model: SOP-20, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 2.65 mm nominal SOIC height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
tc74hc273af-etched.step/tc74hc273af-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc74hc273af.step/tc74hc273af.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (8 pp, sha256
8f6aa2002ada1c33, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).