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TC74HC02APF
Public Made by Adomby adom
TOSHIBA Logic Gates, DIP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTC74HC02APF
TOSHIBA · Logic Gates · DIP-14
TC74HC02APF from TOSHIBA, in a DIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | 1Y | output | Gate 1 NOR output, drives 10 LSTTL loads with |
| 2 | 1A | input | Gate 1 input A; unused inputs must be tied to VCC or GND. |
| 3 | 1B | input | Gate 1 input B; unused inputs must be tied to VCC or GND. |
| 4 | 2Y | output | Gate 2 NOR output, drives 10 LSTTL loads with |
| 5 | 2A | input | Gate 2 input A; unused inputs must be tied to VCC or GND. |
| 6 | 2B | input | Gate 2 input B; unused inputs must be tied to VCC or GND. |
| 7 | GND | power_in | Ground (0 V) supply pin. |
| 8 | 3A | input | Gate 3 input A; unused inputs must be tied to VCC or GND. |
| 9 | 3B | input | Gate 3 input B; unused inputs must be tied to VCC or GND. |
| 10 | 3Y | output | Gate 3 NOR output, drives 10 LSTTL loads with |
| 11 | 4A | input | Gate 4 input A; unused inputs must be tied to VCC or GND. |
| 12 | 4B | input | Gate 4 input B; unused inputs must be tied to VCC or GND. |
| 13 | 4Y | output | Gate 4 NOR output, drives 10 LSTTL loads with |
| 14 | VCC | power_in | Positive supply, operating range 2 to 6 V (absolute maximum 7 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | DIP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage range | VCC | -0.5 | 7 | V | 2 | ||
| DC input voltage | VIN | -0.5 | V | upper limit printed as VCC + 0.5 V | 2 | ||
| DC output voltage | VOUT | -0.5 | V | upper limit printed as VCC + 0.5 V | 2 | ||
| Input diode current | IIK | -20 | 20 | mA | 2 | ||
| Output diode current | IOK | -20 | 20 | mA | 2 | ||
| DC output current | IOUT | -25 | 25 | mA | 2 | ||
| DC VCC/ground current | ICC | -50 | 50 | mA | 2 | ||
| Power dissipation (DIP) | PD | 500 | mW | DIP; Ta = −40~65°C (Note 2) | 2 | ||
| Storage temperature | Tstg | -65 | 150 | °C | 2 | ||
| Supply voltage | VCC | 2 | 6 | V | 2 | ||
| Operating temperature | Topr | -40 | 85 | °C | 2 | ||
| Input rise and fall time | tr, tf | 0 | 1000 | ns | VCC = 2.0 V | 2 | |
| Input rise and fall time | tr, tf | 0 | 500 | ns | VCC = 4.5 V | 2 | |
| Input rise and fall time | tr, tf | 0 | 400 | ns | VCC = 6.0 V | 2 | |
| High-level input voltage | VIH | 1.5 | V | VCC = 2.0 V; Ta = 25°C | 3 | ||
| High-level input voltage | VIH | 3.15 | V | VCC = 4.5 V; Ta = 25°C | 3 | ||
| High-level input voltage | VIH | 4.2 | V | VCC = 6.0 V; Ta = 25°C | 3 | ||
| Low-level input voltage | VIL | 0.5 | V | VCC = 2.0 V; Ta = 25°C | 3 | ||
| Low-level input voltage | VIL | 1.35 | V | VCC = 4.5 V; Ta = 25°C | 3 | ||
| Low-level input voltage | VIL | 1.8 | V | VCC = 6.0 V; Ta = 25°C | 3 | ||
| High-level output voltage | VOH | 1.9 | 2 | V | VIN = VIH or VIL; IOH = −20 μA; VCC = 2.0 V; Ta = 25°C | 3 | |
| High-level output voltage | VOH | 4.4 | 4.5 | V | VIN = VIH or VIL; IOH = −20 μA; VCC = 4.5 V; Ta = 25°C | 3 | |
| High-level output voltage | VOH | 5.9 | 6 | V | VIN = VIH or VIL; IOH = −20 μA; VCC = 6.0 V; Ta = 25°C | 3 | |
| High-level output voltage | VOH | 4.4 | V | VIN = VIH or VIL; IOH = −20 μA; VCC = 4.5 V; Ta = −40~85°C | 3 | ||
| High-level output voltage | VOH | 5.9 | V | VIN = VIH or VIL; IOH = −20 μA; VCC = 6.0 V; Ta = −40~85°C | 3 | ||
| High-level output voltage | VOH | 4.18 | 4.31 | V | VIN = VIH or VIL; IOH = −4 mA; VCC = 4.5 V; Ta = 25°C | 3 | |
| High-level output voltage | VOH | 4.13 | V | VIN = VIH or VIL; IOH = −4 mA; VCC = 4.5 V; Ta = −40~85°C | 3 | ||
| High-level output voltage | VOH | 5.68 | 5.8 | V | VIN = VIH or VIL; IOH = −5.2 mA; VCC = 6.0 V; Ta = 25°C | 3 | |
| High-level output voltage | VOH | 5.63 | V | VIN = VIH or VIL; IOH = −5.2 mA; VCC = 6.0 V; Ta = −40~85°C | 3 | ||
| Low-level output voltage | VOL | 0 | 0.1 | V | VIN = VIH or VIL; IOL = 20 μA; VCC = 2.0 V; Ta = 25°C | 3 | |
| Low-level output voltage | VOL | 0.17 | 0.26 | V | VIN = VIH or VIL; IOL = 4 mA; VCC = 4.5 V; Ta = 25°C | 3 | |
| Low-level output voltage | VOL | 0.33 | V | VIN = VIH or VIL; IOL = 4 mA; VCC = 4.5 V; Ta = −40~85°C | 3 | ||
| Low-level output voltage | VOL | 0.18 | 0.26 | V | VIN = VIH or VIL; IOL = 5.2 mA; VCC = 6.0 V; Ta = 25°C | 3 | |
| Input leakage current | IIN | -0.1 | 0.1 | μA | VIN = VCC or GND; VCC = 6.0 V; Ta = 25°C | 3 | |
| Input leakage current | IIN | -1 | 1 | μA | VIN = VCC or GND; VCC = 6.0 V; Ta = −40~85°C | 3 | |
| Quiescent supply current | ICC | 1 | μA | VIN = VCC or GND; VCC = 6.0 V; Ta = 25°C | 3 | ||
| Quiescent supply current | ICC | 10 | μA | VIN = VCC or GND; VCC = 6.0 V; Ta = −40~85°C | 3 | ||
| Output transition time | tTLH, tTHL | 4 | 8 | ns | CL = 15 pF; VCC = 5 V; Ta = 25°C; input tr = tf = 6 ns | 3 | |
| Propagation delay time | tpLH, tpHL | 6 | 12 | ns | CL = 15 pF; VCC = 5 V; Ta = 25°C; input tr = tf = 6 ns | 3 | |
| Output transition time | tTLH, tTHL | 25 | 75 | ns | CL = 50 pF; VCC = 2.0 V; Ta = 25°C; input tr = tf = 6 ns | 4 | |
| Output transition time | tTLH, tTHL | 7 | 15 | ns | CL = 50 pF; VCC = 4.5 V; Ta = 25°C; input tr = tf = 6 ns | 4 | |
| Output transition time | tTLH, tTHL | 6 | 13 | ns | CL = 50 pF; VCC = 6.0 V; Ta = 25°C; input tr = tf = 6 ns | 4 | |
| Output transition time | tTLH, tTHL | 95 | ns | CL = 50 pF; VCC = 2.0 V; Ta = −40~85°C; input tr = tf = 6 ns | 4 | ||
| Output transition time | tTLH, tTHL | 19 | ns | CL = 50 pF; VCC = 4.5 V; Ta = −40~85°C; input tr = tf = 6 ns | 4 | ||
| Output transition time | tTLH, tTHL | 16 | ns | CL = 50 pF; VCC = 6.0 V; Ta = −40~85°C; input tr = tf = 6 ns | 4 | ||
| Propagation delay time | tpLH, tpHL | 27 | 75 | ns | CL = 50 pF; VCC = 2.0 V; Ta = 25°C; input tr = tf = 6 ns | 4 | |
| Propagation delay time | tpLH, tpHL | 9 | 15 | ns | CL = 50 pF; VCC = 4.5 V; Ta = 25°C; input tr = tf = 6 ns | 4 | |
| Propagation delay time | tpLH, tpHL | 8 | 13 | ns | CL = 50 pF; VCC = 6.0 V; Ta = 25°C; input tr = tf = 6 ns | 4 | |
| Propagation delay time | tpLH, tpHL | 95 | ns | CL = 50 pF; VCC = 2.0 V; Ta = −40~85°C; input tr = tf = 6 ns | 4 | ||
| Propagation delay time | tpLH, tpHL | 19 | ns | CL = 50 pF; VCC = 4.5 V; Ta = −40~85°C; input tr = tf = 6 ns | 4 | ||
| Propagation delay time | tpLH, tpHL | 16 | ns | CL = 50 pF; VCC = 6.0 V; Ta = −40~85°C; input tr = tf = 6 ns | 4 |
CAD (KiCad official)
- Symbol:
TC74HC02APF - Footprint:
Package_DIP:DIP-14_W7.62mm - 3D model: DIP-14 (KiCad packages3D, STEP)
- 3D model files:
tc74hc02apf-etched.step/tc74hc02apf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc74hc02apf.step/tc74hc02apf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (8 pp, sha256
a0a5d942609e493a, retrieved 2026-10-16, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).