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TC74ACT574FTEL

Public Made by Adom

by adom

TOSHIBA Flip Flops, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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TC74ACT574FTEL

TOSHIBA · Flip Flops · TSSOP-20

TC74ACT574FTEL from TOSHIBA, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE input Active-low output enable; when OE is high all eight outputs are forced to the high-impedance state.
2 D0 input Data input to flip-flop 0, compatible with TTL, NMOS and CMOS output levels.
3 D1 input Data input to flip-flop 1, compatible with TTL, NMOS and CMOS output levels.
4 D2 input Data input to flip-flop 2, compatible with TTL, NMOS and CMOS output levels.
5 D3 input Data input to flip-flop 3, compatible with TTL, NMOS and CMOS output levels.
6 D4 input Data input to flip-flop 4, compatible with TTL, NMOS and CMOS output levels.
7 D5 input Data input to flip-flop 5, compatible with TTL, NMOS and CMOS output levels.
8 D6 input Data input to flip-flop 6, compatible with TTL, NMOS and CMOS output levels.
9 D7 input Data input to flip-flop 7, compatible with TTL, NMOS and CMOS output levels.
10 GND power_in Ground reference; unused inputs must be tied to either VCC or GND.
11 CK input Clock input that loads the D inputs into the flip-flops; minimum pulse width is 5.0 ns at VCC = 5 V.
12 Q7 tri_state Three-state output of flip-flop 7; can drive 50 Ω transmission lines with
13 Q6 tri_state Three-state output of flip-flop 6; can drive 50 Ω transmission lines with
14 Q5 tri_state Three-state output of flip-flop 5; can drive 50 Ω transmission lines with
15 Q4 tri_state Three-state output of flip-flop 4; can drive 50 Ω transmission lines with
16 Q3 tri_state Three-state output of flip-flop 3; can drive 50 Ω transmission lines with
17 Q2 tri_state Three-state output of flip-flop 2; can drive 50 Ω transmission lines with
18 Q1 tri_state Three-state output of flip-flop 1; can drive 50 Ω transmission lines with
19 Q0 tri_state Three-state output of flip-flop 0; can drive 50 Ω transmission lines with
20 VCC power_in Supply voltage; recommended operating range 4.5 to 5.5 V, absolute maximum −0.5 to 7.0 V.

Key specifications

Parameter Value
Manufacturer TOSHIBA
Package TSSOP-20
Category Logic
Pins 20

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage range VCC -0.5 7 V 3
DC input voltage VIN -0.5 V upper limit printed as VCC + 0.5 V 3
DC output voltage VOUT -0.5 V upper limit printed as VCC + 0.5 V 3
Input diode current IIK -20 20 mA 3
Output diode current IOK -50 50 mA 3
DC output current IOUT -50 50 mA 3
DC VCC/ground current ICC -200 200 mA 3
Power dissipation PD 180 mW SOP/TSSOP package 3
Storage temperature Tstg -65 150 °C 3
Supply voltage VCC 4.5 5.5 V 3
Input voltage VIN 0 V upper limit printed as VCC 3
Output voltage VOUT 0 V upper limit printed as VCC 3
Operating temperature Topr -40 85 °C 3
Input rise and fall time dt/dV 0 10 ns/V 3
High-level input voltage VIH 2 V VCC = 4.5 to 5.5 V 4
Low-level input voltage VIL 0.8 V VCC = 4.5 to 5.5 V 4
High-level output voltage VOH 4.4 4.5 V VIN = VIH or VIL; IOH = −50 μA; VCC = 4.5 V 4
High-level output voltage VOH 3.8 V VIN = VIH or VIL; IOH = −24 mA; VCC = 4.5 V 4
High-level output voltage VOH 3.85 V VIN = VIH or VIL; IOH = −75 mA (Note); VCC = 5.5 V 4
Low-level output voltage VOL 0 0.1 V VIN = VIH or VIL; IOL = 50 μA; VCC = 4.5 V 4
Low-level output voltage VOL 0.44 V VIN = VIH or VIL; IOL = 24 mA; VCC = 4.5 V 4
Low-level output voltage VOL 1.65 V VIN = VIH or VIL; IOL = 75 mA (Note); VCC = 5.5 V 4
3-state output off-state current IOZ -5 5 μA VIN = VIH or VIL; VOUT = VCC or GND; VCC = 5.5 V 4
Input leakage current IIN -1 1 μA VIN = VCC or GND; VCC = 5.5 V 4
Quiescent supply current ICC 80 μA VIN = VCC or GND; VCC = 5.5 V 4
Quiescent supply current (per input) IC 1.5 mA Per input: VIN = 3.4 V; Other input: VCC or GND; VCC = 5.5 V 4
Minimum pulse width (CK) tw(H), tw(L) 5 ns VCC = 5.0 ± 0.5 V; input tr = tf = 3 ns 4
Minimum set-up time ts 3 ns VCC = 5.0 ± 0.5 V; input tr = tf = 3 ns 4
Minimum hold time th 2 ns VCC = 5.0 ± 0.5 V; input tr = tf = 3 ns 4
Propagation delay time (CK-Q) tpLH, tpHL 1 6.2 11.5 ns CL = 50 pF, RL = 500 Ω; VCC = 5.0 ± 0.5 V; input tr = tf = 3 ns 5
Output enable time tpZL, tpZH 1 6.3 12 ns CL = 50 pF, RL = 500 Ω; VCC = 5.0 ± 0.5 V; input tr = tf = 3 ns 5
Output disable time tpLZ, tpHZ 1 6.6 11 ns CL = 50 pF, RL = 500 Ω; VCC = 5.0 ± 0.5 V; input tr = tf = 3 ns 5
Maximum clock frequency fmax 85 160 MHz VCC = 5.0 ± 0.5 V 5
Input capacitance CIN 5 10 pF 5

CAD (KiCad official)

  • Symbol: TC74ACT574FTEL
  • Footprint: Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm
  • 3D model: TSSOP-20 (KiCad packages3D, STEP)
  • 3D model files: tc74act574ftel-etched.step / tc74act574ftel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tc74act574ftel.step / tc74act574ftel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: TOSHIBA datasheet (9 pp, sha256 3560520bc0c95b6c, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF