component
TC6320TG-G
Public Made by Adomby adom
Microchip Tech MOSFETs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TC6320TG-G
Microchip Tech · MOSFETs · SOIC-8
TC6320TG-G from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SN | passive | Source terminal of the N-channel MOSFET; the N-channel device is rated for a drain-to-source breakdown voltage (BVDSS) of 200 V minimum. |
| 2 | GN | input | Gate of the N-channel MOSFET, with an integrated gate-to-source shunt resistor of 10 to 50 kΩ and a gate-to-source Zener clamp of 13.2 to 25 V. |
| 3 | SP | passive | Source terminal of the P-channel MOSFET; the P-channel device is rated for a drain-to-source breakdown voltage (BVDSS) of -200 V minimum. |
| 4 | GP | input | Gate of the P-channel MOSFET, with an integrated gate-to-source shunt resistor of 10 to 50 kΩ and a gate-to-source Zener clamp of 13.2 to 25 V. |
| 5 | DP | passive | Drain of the P-channel MOSFET; the datasheet lists DP on both pin 5 and pin 6, and the P-channel BVDSS is -200 V minimum. |
| 6 | DP | passive | Drain of the P-channel MOSFET; the datasheet lists DP on both pin 5 and pin 6, and the P-channel BVDSS is -200 V minimum. |
| 7 | DN | passive | Drain of the N-channel MOSFET; the datasheet lists DN on both pin 7 and pin 8, and the N-channel BVDSS is 200 V minimum. |
| 8 | DN | passive | Drain of the N-channel MOSFET; the datasheet lists DN on both pin 7 and pin 8, and the N-channel BVDSS is 200 V minimum. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-source Breakdown Voltage (N-channel) | BVDSS | 200 | V | VGS = 0V, ID = 2 mA | 4 | ||
| Drain-to-source Breakdown Voltage (P-channel) | BVDSS | -200 | V | VGS = 0V, ID = -2 mA | 5 | ||
| Gate Threshold Voltage (N-channel) | VGS(th) | 1 | 2 | V | VGS = VDS, ID = 1 mA | 4 | |
| Gate Threshold Voltage (P-channel) | VGS(th) | -1 | -2.4 | V | VGS = VDS, ID = -1 mA | 5 | |
| Change in VGS(th) with Temperature (N-channel) | ∆VGS(th) | -4.5 | mV/°C | VGS = VDS, ID = 1 mA (Note 2) | 4 | ||
| Change in VGS(th) with Temperature (P-channel) | ∆VGS(th) | 4.5 | mV/°C | VGS = VDS, ID = -1 mA (Note 2) | 5 | ||
| Gate-to-source Shunt Resistor (N-channel) | RGS | 10 | 50 | kΩ | IGS = 100 µA | 4 | |
| Gate-to-source Shunt Resistor (P-channel) | RGS | 10 | 50 | kΩ | IGS = 100 µA | 5 | |
| Gate-to-Source Zener Voltage (N-channel) | VZGS | 13.2 | 25 | V | IGS = 2 mA | 4 | |
| Gate-to-Source Zener Voltage (P-channel) | VZGS | 13.2 | 25 | V | IGS = -2 mA | 5 | |
| Zero-gate Voltage Drain Current (N-channel) | IDSS | 10 | µA | VDS = Maximum rating, VGS = 0V | 4 | ||
| Zero-gate Voltage Drain Current (N-channel, 125°C) | IDSS | 1 | mA | VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) | 4 | ||
| Zero-gate Voltage Drain Current (P-channel) | IDSS | -10 | µA | VDS = Maximum rating, VGS = 0V | 5 | ||
| Zero-gate Voltage Drain Current (P-channel, 125°C) | IDSS | -1 | mA | VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) | 5 | ||
| On-state Drain Current (N-channel) | ID(ON) | 1 | A | VGS = 4.5V, VDS = 25V | 4 | ||
| On-state Drain Current (N-channel) | ID(ON) | 2 | A | VGS = 10V, VDS = 25V | 4 | ||
| On-state Drain Current (P-channel) | ID(ON) | -1 | A | VGS = -4.5V, VDS = -25V | 5 | ||
| On-state Drain Current (P-channel) | ID(ON) | -2 | A | VGS = -10V, VDS = -25V | 5 | ||
| Static Drain-to-source On-state Resistance (N-channel) | RDS(ON) | 8 | Ω | VGS = 4.5V, ID = 150 mA | 4 | ||
| Static Drain-to-source On-state Resistance (N-channel) | RDS(ON) | 7 | Ω | VGS = 10V, ID = 1A | 4 | ||
| Static Drain-to-source On-state Resistance (P-channel) | RDS(ON) | 10 | Ω | VGS = -4.5V, ID = -150 mA | 5 | ||
| Static Drain-to-source On-state Resistance (P-channel) | RDS(ON) | 8 | Ω | VGS = -10V, ID = -1A | 5 | ||
| Change in RDS(ON) with Temperature (N-channel) | ∆RDS(ON) | 1 | %/°C | VGS = 4.5V, ID = 150 mA (Note 2) | 4 | ||
| Change in RDS(ON) with Temperature (P-channel) | ∆RDS(ON) | 1 | %/°C | VGS = -10V, ID = -200 mA (Note 2) | 5 | ||
| Forward Transconductance (N-channel) | GFS | 400 | mmho | VDS = 25V, ID = 500 mA | 4 | ||
| Forward Transconductance (P-channel) | GFS | 400 | mmho | VDS = -25V, ID = -500 mA | 5 | ||
| Input Capacitance (N-channel) | CISS | 110 | pF | VGS = 0V, VDS = 25V, f = 1 MHz | 4 | ||
| Input Capacitance (P-channel) | CISS | 200 | pF | VGS = 0V, VDS = -25V, f = 1 MHz | 5 | ||
| Common Source Output Capacitance (N-channel) | COSS | 60 | pF | 4 | |||
| Common Source Output Capacitance (P-channel) | COSS | 55 | pF | 5 | |||
| Reverse Transfer Capacitance (N-channel) | CRSS | 23 | pF | 4 | |||
| Reverse Transfer Capacitance (P-channel) | CRSS | 30 | pF | 5 | |||
| Turn-on Delay Time (N-channel) | td(ON) | 10 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 | ||
| Turn-on Delay Time (P-channel) | td(ON) | 10 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 | ||
| Rise Time (N-channel) | tr | 15 | ns | 4 | |||
| Rise Time (P-channel) | tr | 15 | ns | 5 | |||
| Turn-off Delay Time (N-channel) | td(OFF) | 20 | ns | 4 | |||
| Turn-off Delay Time (P-channel) | td(OFF) | 20 | ns | 5 | |||
| Fall Time (N-channel) | tf | 15 | ns | 4 | |||
| Fall Time (P-channel) | tf | 15 | ns | 5 | |||
| Diode Forward Voltage Drop (N-channel) | VSD | 1.8 | V | VGS = 0V, ISD = 500 mA (Note 1) | 4 | ||
| Diode Forward Voltage Drop (P-channel) | VSD | -1.8 | V | VGS = 0V, ISD = -500 mA (Note 1) | 5 | ||
| Operating Ambient Temperature | TA | -55 | 150 | °C | 5 | ||
| Storage Temperature | TS | -55 | 150 | °C | 5 | ||
| Package thermal resistance, junction-to-ambient, 8-lead SOIC | JA | 101 | °C/W | Note 1: 1 oz., four-layer, 3" x 4" PCB | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Pin Number Pin Name Description 1 SN Source N-channel | 6 |
CAD (KiCad official)
- Symbol:
TC6320TG-G - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tc6320tg-g-etched.step/tc6320tg-g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc6320tg-g.step/tc6320tg-g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (14 pp, sha256
c4a64fcab98db265, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TC6320TG-G
**Microchip Tech** · MOSFETs · SOIC-8
TC6320TG-G from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SN | passive | Source terminal of the N-channel MOSFET; the N-channel device is rated for a drain-to-source breakdown voltage (BVDSS) of 200 V minimum. |
| 2 | GN | input | Gate of the N-channel MOSFET, with an integrated gate-to-source shunt resistor of 10 to 50 kΩ and a gate-to-source Zener clamp of 13.2 to 25 V. |
| 3 | SP | passive | Source terminal of the P-channel MOSFET; the P-channel device is rated for a drain-to-source breakdown voltage (BVDSS) of -200 V minimum. |
| 4 | GP | input | Gate of the P-channel MOSFET, with an integrated gate-to-source shunt resistor of 10 to 50 kΩ and a gate-to-source Zener clamp of 13.2 to 25 V. |
| 5 | DP | passive | Drain of the P-channel MOSFET; the datasheet lists DP on both pin 5 and pin 6, and the P-channel BVDSS is -200 V minimum. |
| 6 | DP | passive | Drain of the P-channel MOSFET; the datasheet lists DP on both pin 5 and pin 6, and the P-channel BVDSS is -200 V minimum. |
| 7 | DN | passive | Drain of the N-channel MOSFET; the datasheet lists DN on both pin 7 and pin 8, and the N-channel BVDSS is 200 V minimum. |
| 8 | DN | passive | Drain of the N-channel MOSFET; the datasheet lists DN on both pin 7 and pin 8, and the N-channel BVDSS is 200 V minimum. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Transistors/Thyristors |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-to-source Breakdown Voltage (N-channel) | BVDSS | 200 | | | V | VGS = 0V, ID = 2 mA | 4 |
| Drain-to-source Breakdown Voltage (P-channel) | BVDSS | -200 | | | V | VGS = 0V, ID = -2 mA | 5 |
| Gate Threshold Voltage (N-channel) | VGS(th) | 1 | | 2 | V | VGS = VDS, ID = 1 mA | 4 |
| Gate Threshold Voltage (P-channel) | VGS(th) | -1 | | -2.4 | V | VGS = VDS, ID = -1 mA | 5 |
| Change in VGS(th) with Temperature (N-channel) | ∆VGS(th) | | | -4.5 | mV/°C | VGS = VDS, ID = 1 mA (Note 2) | 4 |
| Change in VGS(th) with Temperature (P-channel) | ∆VGS(th) | | | 4.5 | mV/°C | VGS = VDS, ID = -1 mA (Note 2) | 5 |
| Gate-to-source Shunt Resistor (N-channel) | RGS | 10 | | 50 | kΩ | IGS = 100 µA | 4 |
| Gate-to-source Shunt Resistor (P-channel) | RGS | 10 | | 50 | kΩ | IGS = 100 µA | 5 |
| Gate-to-Source Zener Voltage (N-channel) | VZGS | 13.2 | | 25 | V | IGS = 2 mA | 4 |
| Gate-to-Source Zener Voltage (P-channel) | VZGS | 13.2 | | 25 | V | IGS = -2 mA | 5 |
| Zero-gate Voltage Drain Current (N-channel) | IDSS | | | 10 | µA | VDS = Maximum rating, VGS = 0V | 4 |
| Zero-gate Voltage Drain Current (N-channel, 125°C) | IDSS | | | 1 | mA | VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) | 4 |
| Zero-gate Voltage Drain Current (P-channel) | IDSS | | | -10 | µA | VDS = Maximum rating, VGS = 0V | 5 |
| Zero-gate Voltage Drain Current (P-channel, 125°C) | IDSS | | | -1 | mA | VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) | 5 |
| On-state Drain Current (N-channel) | ID(ON) | 1 | | | A | VGS = 4.5V, VDS = 25V | 4 |
| On-state Drain Current (N-channel) | ID(ON) | 2 | | | A | VGS = 10V, VDS = 25V | 4 |
| On-state Drain Current (P-channel) | ID(ON) | -1 | | | A | VGS = -4.5V, VDS = -25V | 5 |
| On-state Drain Current (P-channel) | ID(ON) | -2 | | | A | VGS = -10V, VDS = -25V | 5 |
| Static Drain-to-source On-state Resistance (N-channel) | RDS(ON) | | | 8 | Ω | VGS = 4.5V, ID = 150 mA | 4 |
| Static Drain-to-source On-state Resistance (N-channel) | RDS(ON) | | | 7 | Ω | VGS = 10V, ID = 1A | 4 |
| Static Drain-to-source On-state Resistance (P-channel) | RDS(ON) | | | 10 | Ω | VGS = -4.5V, ID = -150 mA | 5 |
| Static Drain-to-source On-state Resistance (P-channel) | RDS(ON) | | | 8 | Ω | VGS = -10V, ID = -1A | 5 |
| Change in RDS(ON) with Temperature (N-channel) | ∆RDS(ON) | | | 1 | %/°C | VGS = 4.5V, ID = 150 mA (Note 2) | 4 |
| Change in RDS(ON) with Temperature (P-channel) | ∆RDS(ON) | | | 1 | %/°C | VGS = -10V, ID = -200 mA (Note 2) | 5 |
| Forward Transconductance (N-channel) | GFS | 400 | | | mmho | VDS = 25V, ID = 500 mA | 4 |
| Forward Transconductance (P-channel) | GFS | 400 | | | mmho | VDS = -25V, ID = -500 mA | 5 |
| Input Capacitance (N-channel) | CISS | | | 110 | pF | VGS = 0V, VDS = 25V, f = 1 MHz | 4 |
| Input Capacitance (P-channel) | CISS | | | 200 | pF | VGS = 0V, VDS = -25V, f = 1 MHz | 5 |
| Common Source Output Capacitance (N-channel) | COSS | | | 60 | pF | | 4 |
| Common Source Output Capacitance (P-channel) | COSS | | | 55 | pF | | 5 |
| Reverse Transfer Capacitance (N-channel) | CRSS | | | 23 | pF | | 4 |
| Reverse Transfer Capacitance (P-channel) | CRSS | | | 30 | pF | | 5 |
| Turn-on Delay Time (N-channel) | td(ON) | | | 10 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 |
| Turn-on Delay Time (P-channel) | td(ON) | | | 10 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 |
| Rise Time (N-channel) | tr | | | 15 | ns | | 4 |
| Rise Time (P-channel) | tr | | | 15 | ns | | 5 |
| Turn-off Delay Time (N-channel) | td(OFF) | | | 20 | ns | | 4 |
| Turn-off Delay Time (P-channel) | td(OFF) | | | 20 | ns | | 5 |
| Fall Time (N-channel) | tf | | | 15 | ns | | 4 |
| Fall Time (P-channel) | tf | | | 15 | ns | | 5 |
| Diode Forward Voltage Drop (N-channel) | VSD | | | 1.8 | V | VGS = 0V, ISD = 500 mA (Note 1) | 4 |
| Diode Forward Voltage Drop (P-channel) | VSD | | | -1.8 | V | VGS = 0V, ISD = -500 mA (Note 1) | 5 |
| Operating Ambient Temperature | TA | -55 | | 150 | °C | | 5 |
| Storage Temperature | TS | -55 | | 150 | °C | | 5 |
| Package thermal resistance, junction-to-ambient, 8-lead SOIC | JA | | 101 | | °C/W | Note 1: 1 oz., four-layer, 3" x 4" PCB | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | Pin Number Pin Name Description 1 SN Source N-channel | 6 |
## CAD (KiCad official)
- Symbol: `TC6320TG-G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tc6320tg-g-etched.step` / `tc6320tg-g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tc6320tg-g.step` / `tc6320tg-g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588914730261467136) (14 pp, sha256 `c4a64fcab98db265`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tc6320tg-g-datasheet.pdf)