component
TC6320K6-G
Public Made by Adomby adom
Microchip Tech MOSFETs, DFN-8-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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TC6320K6-G
Microchip Tech · MOSFETs · DFN-8-EP(4x4)
TC6320K6-G from Microchip Tech, in a DFN-8-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SN | passive | Source of the N-channel MOSFET (BVDSS 200 V, RDS(ON) max 7 Ω). |
| 2 | GN | passive | Gate of the N-channel MOSFET, with integrated 10-50 kΩ gate-to-source resistor and 13.2-25 V gate-to-source Zener clamp. |
| 3 | GP | passive | Gate of the P-channel MOSFET, with integrated 10-50 kΩ gate-to-source resistor and 13.2-25 V gate-to-source Zener clamp. |
| 4 | SP | passive | Source of the P-channel MOSFET (BVDSS -200 V, RDS(ON) max 8 Ω). |
| 5 | DP | passive | Drain of the P-channel MOSFET (BVDSS -200 V); tied internally with pin 6. |
| 6 | DP | passive | Drain of the P-channel MOSFET (BVDSS -200 V); tied internally with pin 5. |
| 7 | DN | passive | Drain of the N-channel MOSFET (BVDSS 200 V); tied internally with pin 8. |
| 8 | DN | passive | Drain of the N-channel MOSFET (BVDSS 200 V); tied internally with pin 7. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DFN-8-EP(4x4) |
| Category | Triode/MOS Tube/Transistor |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| N-ch Drain-to-source Breakdown Voltage | BVDSS | 200 | V | VGS = 0V, ID = 2 mA | 4 | ||
| N-ch Gate Threshold Voltage | VGS(th) | 1 | 2 | V | VGS = VDS, ID = 1 mA | 4 | |
| N-ch Change in VGS(th) with Temperature | ΔVGS(th) | -4.5 | mV/°C | VGS = VDS, ID = 1 mA (Note 2) | 4 | ||
| N-ch Gate-to-source Shunt Resistor | RGS | 10 | 50 | kΩ | IGS = 100 µA | 4 | |
| N-ch Gate-to-Source Zener Voltage | VZGS | 13.2 | 25 | V | IGS = 2 mA | 4 | |
| N-ch Zero-gate Voltage Drain Current | IDSS | 10 | µA | VDS = Maximum rating, VGS = 0V | 4 | ||
| N-ch Zero-gate Voltage Drain Current (125°C) | IDSS | 1 | mA | VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) | 4 | ||
| N-ch On-state Drain Current | ID(ON) | 1 | A | VGS = 4.5V, VDS = 25V | 4 | ||
| N-ch On-state Drain Current | ID(ON) | 2 | A | VGS = 10V, VDS = 25V | 4 | ||
| N-ch Static Drain-to-source On-state Resistance | RDS(ON) | 8 | Ω | VGS = 4.5V, ID = 150 mA | 4 | ||
| N-ch Static Drain-to-source On-state Resistance | RDS(ON) | 7 | Ω | VGS = 10V, ID = 1A | 4 | ||
| N-ch Change in RDS(ON) with Temperature | ΔRDS(ON) | 1 | %/°C | VGS = 4.5V, ID = 150 mA (Note 2) | 4 | ||
| N-ch Forward Transconductance | GFS | 400 | mmho | VDS = 25V, ID = 500 mA | 4 | ||
| N-ch Input Capacitance | CISS | 110 | pF | VGS = 0V, VDS = 25V, f = 1 MHz | 4 | ||
| N-ch Common Source Output Capacitance | COSS | 60 | pF | VGS = 0V, VDS = 25V, f = 1 MHz | 4 | ||
| N-ch Reverse Transfer Capacitance | CRSS | 23 | pF | VGS = 0V, VDS = 25V, f = 1 MHz | 4 | ||
| N-ch Turn-on Delay Time | td(ON) | 10 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 | ||
| N-ch Rise Time | tr | 15 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 | ||
| N-ch Turn-off Delay Time | td(OFF) | 20 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 | ||
| N-ch Fall Time | tf | 15 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 | ||
| N-ch Diode Forward Voltage Drop | VSD | 1.8 | V | VGS = 0V, ISD = 500 mA (Note 1) | 4 | ||
| N-ch Reverse Recovery Time | trr | 300 | ns | VGS = 0V, ISD = 500 mA (Note 2) | 4 | ||
| P-ch Drain-to-source Breakdown Voltage | BVDSS | -200 | V | VGS = 0V, ID = -2 mA | 5 | ||
| P-ch Gate Threshold Voltage | VGS(th) | -1 | -2.4 | V | VGS = VDS, ID = -1 mA | 5 | |
| P-ch Change in VGS(th) with Temperature | ΔVGS(th) | 4.5 | mV/°C | VGS = VDS, ID = -1 mA (Note 2) | 5 | ||
| P-ch Gate-to-source Shunt Resistor | RGS | 10 | 50 | kΩ | IGS = 100 µA | 5 | |
| P-ch Gate-to-Source Zener Voltage | VZGS | 13.2 | 25 | V | IGS = -2 mA | 5 | |
| P-ch Zero-gate Voltage Drain Current | IDSS | -10 | µA | VDS = Maximum rating, VGS = 0V | 5 | ||
| P-ch Zero-gate Voltage Drain Current (125°C) | IDSS | -1 | mA | VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) | 5 | ||
| P-ch On-state Drain Current | ID(ON) | -1 | A | VGS = -4.5V, VDS = -25V | 5 | ||
| P-ch On-state Drain Current | ID(ON) | -2 | A | VGS = -10V, VDS = -25V | 5 | ||
| P-ch Static Drain-to-source On-state Resistance | RDS(ON) | 10 | Ω | VGS = -4.5V, ID = -150 mA | 5 | ||
| P-ch Static Drain-to-source On-state Resistance | RDS(ON) | 8 | Ω | VGS = -10V, ID = -1A | 5 | ||
| P-ch Change in RDS(ON) with Temperature | ΔRDS(ON) | 1 | %/°C | VGS = -10V, ID = -200 mA (Note 2) | 5 | ||
| P-ch Forward Transconductance | GFS | 400 | mmho | VDS = -25V, ID = -500 mA | 5 | ||
| P-ch Input Capacitance | CISS | 200 | pF | VGS = 0V, VDS = -25V, f = 1 MHz | 5 | ||
| P-ch Common Source Output Capacitance | COSS | 55 | pF | VGS = 0V, VDS = -25V, f = 1 MHz | 5 | ||
| P-ch Reverse Transfer Capacitance | CRSS | 30 | pF | VGS = 0V, VDS = -25V, f = 1 MHz | 5 | ||
| P-ch Turn-on Delay Time | td(ON) | 10 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 | ||
| P-ch Rise Time | tr | 15 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 | ||
| P-ch Turn-off Delay Time | td(OFF) | 20 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 | ||
| P-ch Fall Time | tf | 15 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 | ||
| P-ch Diode Forward Voltage Drop | VSD | -1.8 | V | VGS = 0V, ISD = -500 mA (Note 1) | 5 | ||
| P-ch Reverse Recovery Time | trr | 300 | ns | VGS = 0V, ISD = -500 mA (Note 2) | 5 | ||
| Operating Ambient Temperature (absolute maximum) | TA | -55 | 150 | °C | 4 | ||
| Storage Temperature (absolute maximum) | TS | -55 | 150 | °C | 4 | ||
| Operating Ambient Temperature | TA | -55 | 150 | °C | TA = TJ = +25°C unless otherwise specified | 5 | |
| Storage Temperature | TS | -55 | 150 | °C | TA = TJ = +25°C unless otherwise specified | 5 | |
| Package Thermal Resistance, 8-lead DFN | θJA | 44 | °C/W | 1 oz., four-layer, 3” x 4” PCB | 5 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | tin | Pin Number Pin Name Description 1 SN Source N-channel | 6 |
CAD (KiCad official)
- Symbol:
TC6320K6-G - Footprint:
Package_DFN_QFN:DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm - 3D model: DFN-8-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
tc6320k6-g-etched.step/tc6320k6-g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc6320k6-g.step/tc6320k6-g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (14 pp, sha256
211d361f2040a2d0, retrieved 2026-10-22, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# TC6320K6-G
**Microchip Tech** · MOSFETs · DFN-8-EP(4x4)
TC6320K6-G from Microchip Tech, in a DFN-8-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SN | passive | Source of the N-channel MOSFET (BVDSS 200 V, RDS(ON) max 7 Ω). |
| 2 | GN | passive | Gate of the N-channel MOSFET, with integrated 10-50 kΩ gate-to-source resistor and 13.2-25 V gate-to-source Zener clamp. |
| 3 | GP | passive | Gate of the P-channel MOSFET, with integrated 10-50 kΩ gate-to-source resistor and 13.2-25 V gate-to-source Zener clamp. |
| 4 | SP | passive | Source of the P-channel MOSFET (BVDSS -200 V, RDS(ON) max 8 Ω). |
| 5 | DP | passive | Drain of the P-channel MOSFET (BVDSS -200 V); tied internally with pin 6. |
| 6 | DP | passive | Drain of the P-channel MOSFET (BVDSS -200 V); tied internally with pin 5. |
| 7 | DN | passive | Drain of the N-channel MOSFET (BVDSS 200 V); tied internally with pin 8. |
| 8 | DN | passive | Drain of the N-channel MOSFET (BVDSS 200 V); tied internally with pin 7. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | DFN-8-EP(4x4) |
| Category | Triode/MOS Tube/Transistor |
| Pins | 9 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| N-ch Drain-to-source Breakdown Voltage | BVDSS | 200 | | | V | VGS = 0V, ID = 2 mA | 4 |
| N-ch Gate Threshold Voltage | VGS(th) | 1 | | 2 | V | VGS = VDS, ID = 1 mA | 4 |
| N-ch Change in VGS(th) with Temperature | ΔVGS(th) | | | -4.5 | mV/°C | VGS = VDS, ID = 1 mA (Note 2) | 4 |
| N-ch Gate-to-source Shunt Resistor | RGS | 10 | | 50 | kΩ | IGS = 100 µA | 4 |
| N-ch Gate-to-Source Zener Voltage | VZGS | 13.2 | | 25 | V | IGS = 2 mA | 4 |
| N-ch Zero-gate Voltage Drain Current | IDSS | | | 10 | µA | VDS = Maximum rating, VGS = 0V | 4 |
| N-ch Zero-gate Voltage Drain Current (125°C) | IDSS | | | 1 | mA | VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) | 4 |
| N-ch On-state Drain Current | ID(ON) | 1 | | | A | VGS = 4.5V, VDS = 25V | 4 |
| N-ch On-state Drain Current | ID(ON) | 2 | | | A | VGS = 10V, VDS = 25V | 4 |
| N-ch Static Drain-to-source On-state Resistance | RDS(ON) | | | 8 | Ω | VGS = 4.5V, ID = 150 mA | 4 |
| N-ch Static Drain-to-source On-state Resistance | RDS(ON) | | | 7 | Ω | VGS = 10V, ID = 1A | 4 |
| N-ch Change in RDS(ON) with Temperature | ΔRDS(ON) | | | 1 | %/°C | VGS = 4.5V, ID = 150 mA (Note 2) | 4 |
| N-ch Forward Transconductance | GFS | 400 | | | mmho | VDS = 25V, ID = 500 mA | 4 |
| N-ch Input Capacitance | CISS | | | 110 | pF | VGS = 0V, VDS = 25V, f = 1 MHz | 4 |
| N-ch Common Source Output Capacitance | COSS | | | 60 | pF | VGS = 0V, VDS = 25V, f = 1 MHz | 4 |
| N-ch Reverse Transfer Capacitance | CRSS | | | 23 | pF | VGS = 0V, VDS = 25V, f = 1 MHz | 4 |
| N-ch Turn-on Delay Time | td(ON) | | | 10 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 |
| N-ch Rise Time | tr | | | 15 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 |
| N-ch Turn-off Delay Time | td(OFF) | | | 20 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 |
| N-ch Fall Time | tf | | | 15 | ns | VDD = 25V, ID = 1A, RGEN = 25Ω | 4 |
| N-ch Diode Forward Voltage Drop | VSD | | | 1.8 | V | VGS = 0V, ISD = 500 mA (Note 1) | 4 |
| N-ch Reverse Recovery Time | trr | | 300 | | ns | VGS = 0V, ISD = 500 mA (Note 2) | 4 |
| P-ch Drain-to-source Breakdown Voltage | BVDSS | -200 | | | V | VGS = 0V, ID = -2 mA | 5 |
| P-ch Gate Threshold Voltage | VGS(th) | -1 | | -2.4 | V | VGS = VDS, ID = -1 mA | 5 |
| P-ch Change in VGS(th) with Temperature | ΔVGS(th) | | | 4.5 | mV/°C | VGS = VDS, ID = -1 mA (Note 2) | 5 |
| P-ch Gate-to-source Shunt Resistor | RGS | 10 | | 50 | kΩ | IGS = 100 µA | 5 |
| P-ch Gate-to-Source Zener Voltage | VZGS | 13.2 | | 25 | V | IGS = -2 mA | 5 |
| P-ch Zero-gate Voltage Drain Current | IDSS | | | -10 | µA | VDS = Maximum rating, VGS = 0V | 5 |
| P-ch Zero-gate Voltage Drain Current (125°C) | IDSS | | | -1 | mA | VDS = 0.8 Maximum rating, VGS = 0V, TA = 125°C (Note 2) | 5 |
| P-ch On-state Drain Current | ID(ON) | -1 | | | A | VGS = -4.5V, VDS = -25V | 5 |
| P-ch On-state Drain Current | ID(ON) | -2 | | | A | VGS = -10V, VDS = -25V | 5 |
| P-ch Static Drain-to-source On-state Resistance | RDS(ON) | | | 10 | Ω | VGS = -4.5V, ID = -150 mA | 5 |
| P-ch Static Drain-to-source On-state Resistance | RDS(ON) | | | 8 | Ω | VGS = -10V, ID = -1A | 5 |
| P-ch Change in RDS(ON) with Temperature | ΔRDS(ON) | | | 1 | %/°C | VGS = -10V, ID = -200 mA (Note 2) | 5 |
| P-ch Forward Transconductance | GFS | 400 | | | mmho | VDS = -25V, ID = -500 mA | 5 |
| P-ch Input Capacitance | CISS | | | 200 | pF | VGS = 0V, VDS = -25V, f = 1 MHz | 5 |
| P-ch Common Source Output Capacitance | COSS | | | 55 | pF | VGS = 0V, VDS = -25V, f = 1 MHz | 5 |
| P-ch Reverse Transfer Capacitance | CRSS | | | 30 | pF | VGS = 0V, VDS = -25V, f = 1 MHz | 5 |
| P-ch Turn-on Delay Time | td(ON) | | | 10 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 |
| P-ch Rise Time | tr | | | 15 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 |
| P-ch Turn-off Delay Time | td(OFF) | | | 20 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 |
| P-ch Fall Time | tf | | | 15 | ns | VDD = -25V, ID = -1A, RGEN = 25Ω | 5 |
| P-ch Diode Forward Voltage Drop | VSD | | | -1.8 | V | VGS = 0V, ISD = -500 mA (Note 1) | 5 |
| P-ch Reverse Recovery Time | trr | | 300 | | ns | VGS = 0V, ISD = -500 mA (Note 2) | 5 |
| Operating Ambient Temperature (absolute maximum) | TA | -55 | | 150 | °C | | 4 |
| Storage Temperature (absolute maximum) | TS | -55 | | 150 | °C | | 4 |
| Operating Ambient Temperature | TA | -55 | | 150 | °C | TA = TJ = +25°C unless otherwise specified | 5 |
| Storage Temperature | TS | -55 | | 150 | °C | TA = TJ = +25°C unless otherwise specified | 5 |
| Package Thermal Resistance, 8-lead DFN | θJA | | 44 | | °C/W | 1 oz., four-layer, 3” x 4” PCB | 5 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | | tin | Pin Number Pin Name Description 1 SN Source N-channel | 6 |
## CAD (KiCad official)
- Symbol: `TC6320K6-G`
- Footprint: `Package_DFN_QFN:DFN-8-1EP_4x4mm_P0.8mm_EP2.5x3.6mm`
- 3D model: DFN-8-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `tc6320k6-g-etched.step` / `tc6320k6-g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tc6320k6-g.step` / `tc6320k6-g.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Microchip Tech datasheet](docs/tc6320k6-g-datasheet.pdf) (14 pp, sha256 `211d361f2040a2d0`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/tc6320k6-g-datasheet.pdf)