# TC4429CPA

**Microchip Tech** · Gate Drive ICs · PDIP-8

TC4429CPA from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply input rated 4.5V to 18V with respect to ground; bypass with a local ceramic capacitor of at least 1.0 µF, and connect both VDD pins (1 and 8). |
| 2 | INPUT | input | TTL/CMOS compatible high-impedance control input, VIH min 2.4V, VIL max 0.8V, tolerates -5V to VDD+0.3V; avoid slow edges to prevent double-pulsing. |
| 3 | NC | unconnected | No connection. |
| 4 | GND | power_in | Ground return for bias current and high peak load-discharge currents; tie to a ground plane and connect both GND pins (4 and 5). |
| 5 | GND | power_in | Ground return for bias current and high peak load-discharge currents; tie to a ground plane and connect both GND pins (4 and 5). |
| 6 | OUTPUT | output | CMOS push-pull output with 6.0A peak drive, withstands 1.5A reverse current, inverting on TC4429; connect both OUTPUT pins (6 and 7). |
| 7 | OUTPUT | output | CMOS push-pull output with 6.0A peak drive, withstands 1.5A reverse current, inverting on TC4429; connect both OUTPUT pins (6 and 7). |
| 8 | VDD | power_in | Supply input rated 4.5V to 18V with respect to ground; bypass with a local ceramic capacitor of at least 1.0 µF, and connect both VDD pins (1 and 8). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Power Supply Chip |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage |  |  |  | 20 | V |  | 3 |
| Input Voltage (min) |  | -5 |  |  | V | -5V to VDD + 0.3V | 3 |
| Input Current |  |  |  | 50 | mA | VIN > VDD | 3 |
| Logic 1 High Input Voltage | VIH | 2.4 | 1.8 |  | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 3 |
| Logic 0 Low Input Voltage | VIL |  | 1.3 | 0.8 | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 3 |
| Input Voltage Range (min) | VIN | -5 |  |  | V | max is VDD+0.3 | 3 |
| Input Current | IIN | -10 |  | 10 | µA | 0V ≤ VIN ≤ VDD | 3 |
| Low Output Voltage | VOL |  |  | 0.025 | V | DC TEST | 3 |
| Output Resistance, High | ROH |  | 2.1 | 2.8 | Ω | IOUT = 10 mA, VDD = 18V | 3 |
| Output Resistance, Low | ROL |  | 1.5 | 2.5 | Ω | IOUT = 10 mA, VDD = 18V | 3 |
| Peak Output Current | IPK |  | 6 |  | A | VDD = 18V | 3 |
| Rise Time | tR |  | 25 | 35 | ns | Figure 4-1, CL = 2,500 pF | 3 |
| Fall Time | tF |  | 25 | 35 | ns | Figure 4-1, CL = 2,500 pF | 3 |
| Delay Time | tD1 |  | 55 | 75 | ns | Figure 4-1 | 3 |
| Power Supply Current | IS |  | 0.45 | 1.5 | mA | VIN = 3V | 3 |
| Power Supply Current | IS |  | 55 | 150 | µA | VIN = 0V | 3 |
| Operating Input Voltage | VDD | 4.5 |  | 18 | V |  | 3 |
| Logic 1 High Input Voltage (over temp) | VIH | 2.4 |  |  | V | over operating temperature range | 4 |
| Logic 0 Low Input Voltage (over temp) | VIL |  |  | 0.8 | V | over operating temperature range | 4 |
| Input Current (over temp) | IIN | -10 |  | 10 | µA | 0V ≤ VIN ≤ VDD | 4 |
| Low Output Voltage (over temp) | VOL |  |  | 0.025 | V | DC TEST | 4 |
| Output Resistance, Low (over temp) | ROL |  | 2.3 | 5 | Ω | IOUT = 10 mA, VDD = 18V | 4 |
| Rise Time (over temp) | tR |  | 32 | 60 | ns | Figure 4-1, CL = 2,500 pF | 4 |
| Fall Time (over temp) | tF |  | 34 | 60 | ns | Figure 4-1, CL = 2,500 pF | 4 |
| Delay Time (over temp) | tD1 |  | 50 | 100 | ns | Figure 4-1 | 4 |
| Delay Time (over temp) | tD2 |  | 65 | 100 | ns | Figure 4-1 | 4 |
| Power Supply Current (over temp) | IS |  | 0.45 | 3 | mA | VIN = 3V | 4 |
| Power Supply Current (over temp) | IS |  | 60 | 400 | µA | VIN = 0V | 4 |
| Operating Input Voltage (over temp) | VDD | 4.5 |  | 18 | V |  | 4 |
| Specified Temperature Range (C) | TA | 0 |  | 70 | °C |  | 4 |
| Maximum Junction Temperature | TJ |  |  | 150 | °C |  | 4 |
| Storage Temperature Range | TA | -65 |  | 150 | °C |  | 4 |
| Thermal Resistance, 8L-PDIP | θJA |  | 125 |  | °C/W |  | 4 |

## CAD (KiCad official)

- Symbol: `TC4429CPA`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files: `tc4429cpa-etched.step` / `tc4429cpa-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tc4429cpa.step` / `tc4429cpa.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/tc4429cpa-datasheet.pdf) (22 pp, sha256 `1513714315f0665c`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tc4429cpa-datasheet.pdf)