component
TC4424AVOA
Public Made by Adomby adom
Microchip Tech Gate Drive ICs, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
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|---|---|
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| README.md | 8d ago |
| tc4424avoa-etched.glb | 8d ago |
| tc4424avoa-etched.step | 8d ago |
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TC4424AVOA
Microchip Tech · Gate Drive ICs · SOIC-8
TC4424AVOA from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No connection. |
| 2 | IN A | input | TTL/CMOS compatible Input A controlling output A, with 300 mV of hysteresis, input range -5V to VDD+0.3V. |
| 3 | GND | power_in | Ground return pin, should have a low-impedance connection to the bias supply source return since high peak currents flow out of it when the capacitive load is discharged. |
| 4 | IN B | input | TTL/CMOS compatible Input B controlling output B, with 300 mV of hysteresis, input range -5V to VDD+0.3V. |
| 5 | OUT B | output | CMOS push-pull Output B capable of sourcing and sinking 3A peaks (VDD = 18V) with a reverse current latch-up rating of 1.5A. |
| 6 | VDD | power_in | Supply input with a range of 4.5V to 18V that must be decoupled to ground with a local ceramic capacitor. |
| 7 | OUT A | output | CMOS push-pull Output A capable of sourcing and sinking 3A peaks (VDD = 18V) with a reverse current latch-up rating of 1.5A. |
| 8 | NC | unconnected | No connection. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Power Management ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage (absolute maximum) | 20 | V | 3 | ||||
| Package Power Dissipation 8L SOIC | 0.61 | W | TA=50°C | 3 | |||
| Maximum Junction Temperature | TJ | 150 | °C | 4 | |||
| Storage Temperature Range | TA | -65 | 150 | °C | 4 | ||
| Specified Temperature Range (V) | TA | -40 | 125 | °C | 4 | ||
| Supply Voltage | VDD | 4.5 | 18 | V | 3 | ||
| Logic 1 High Input Voltage | VIH | 2.4 | 1.5 | V | TA=+25°C, 4.5V≤VDD≤18V | 3 | |
| Logic 0 Low Input Voltage | VIL | 1.3 | 0.8 | V | TA=+25°C, 4.5V≤VDD≤18V | 3 | |
| Input Current | IIN | -1 | 1 | µA | 0V ≤ VIN ≤ VDD | 3 | |
| Input Voltage | VIN | -5 | V | max printed as VDD+0.3 | 3 | ||
| Low Output Voltage | VOL | 0.025 | V | DC Test | 3 | ||
| Output Resistance, High | ROH | 2.2 | 3 | Ω | IOUT = 10 mA, VDD = 18V | 3 | |
| Output Resistance, Low | ROL | 2.8 | 3.5 | Ω | IOUT = 10 mA, VDD = 18V | 3 | |
| Rise Time | tR | 12 | 21 | ns | Figure 4-1, Figure 4-2, CL = 1800 pF | 3 | |
| Fall Time | tF | 12 | 21 | ns | Figure 4-1, Figure 4-2, CL = 1800 pF | 3 | |
| Delay Time | tD1 | 40 | 48 | ns | Figure 4-1, Figure 4-2, CL = 1800 pF | 3 | |
| Delay Time | tD2 | 41 | 48 | ns | Figure 4-1, Figure 4-2, CL = 1800 pF | 3 | |
| Power Supply Current | IS | 1 | 2 | mA | VIN = 3V (Both inputs) | 3 | |
| Power Supply Current | IS | 0.15 | 0.25 | mA | VIN = 0V (Both inputs) | 3 | |
| Logic 1 High Input Voltage (over temperature) | VIH | 2.4 | V | operating temperature range, 4.5V≤VDD≤18V | 4 | ||
| Logic 0 Low Input Voltage (over temperature) | VIL | 0.8 | V | operating temperature range, 4.5V≤VDD≤18V | 4 | ||
| Input Current (over temperature) | IIN | -10 | 10 | µA | 0V ≤ VIN ≤ VDD | 4 | |
| Low Output Voltage (over temperature) | VOL | 0.025 | V | operating temperature range | 4 | ||
| Output Resistance, High (over temperature) | ROH | 3.1 | 6 | Ω | IOUT = 10 mA, VDD = 18V | 4 | |
| Output Resistance, Low (over temperature) | ROL | 3.7 | 7 | Ω | IOUT = 10 mA, VDD = 18V | 4 | |
| Rise Time (over temperature) | tR | 20 | 31 | ns | Figure 4-1, Figure 4-2, CL = 1800 pF | 4 | |
| Fall Time (over temperature) | tF | 22 | 31 | ns | Figure 4-1, Figure 4-2, CL = 1800 pF | 4 | |
| Delay Time (over temperature) | tD1 | 50 | 66 | ns | Figure 4-1, Figure 4-2, CL = 1800 pF | 4 | |
| Power Supply Current (over temperature) | IS | 2 | 3 | mA | VIN = 3V (Both inputs) | 4 | |
| Power Supply Current (over temperature) | IS | 0.2 | 0.3 | mA | VIN = 0V (Both inputs) | 4 | |
| Peak Output Current | IPK | 4.5 | A | 10V≤ VDD ≤18V (Note 2) | 3 | ||
| Thermal Resistance, 8L-SOIC | θJA | 163 | °C/W | 4 |
CAD (KiCad official)
- Symbol:
TC4424AVOA - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tc4424avoa-etched.step/tc4424avoa-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc4424avoa.step/tc4424avoa.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (22 pp, sha256
c657a9dedbbf331a, retrieved 2026-10-31, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).