# TC426CPA

**Microchip Tech** · Gate Drive ICs · PDIP-8

TC426CPA from Microchip Tech, in a PDIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | NC | unconnected | No internal connection. |
| 2 | IN A | input | Control input A, TTL/CMOS compatible logic input (VIH min 2.4V, VIL max 0.8V); unused inputs must be tied to VDD or GND. |
| 3 | GND | power_in | Ground. |
| 4 | IN B | input | Control input B, TTL/CMOS compatible logic input (VIH min 2.4V, VIL max 0.8V); unused inputs must be tied to VDD or GND. |
| 5 | OUT B | output | CMOS totem-pole output for driver B, with 1.5A peak output current and swing within 25 mV of the rails. |
| 6 | VDD | power_in | Supply input, 4.5V to 18V. |
| 7 | OUT A | output | CMOS totem-pole output for driver A, with 1.5A peak output current and swing within 25 mV of the rails. |
| 8 | NC | unconnected | No internal connection. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | PDIP-8 |
| Category | Power Supply Chip |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic 1, High Input Voltage | VIH | 2.4 |  |  | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 3 |
| Logic 0, Low Input Voltage | VIL |  |  | 0.8 | V | TA = +25°C, 4.5V ≤ VDD ≤ 18V | 3 |
| Input Current | IIN | -1 |  | 1 | µA | 0V ≤ VIN ≤ VDD, TA = +25°C | 3 |
| Low Output Voltage | VOL |  |  | 0.025 | V | TA = +25°C | 3 |
| High Output Resistance | ROH |  | 10 | 15 | Ω | IOUT = 10 mA, VDD = 18V, TA = +25°C | 3 |
| Low Output Resistance | ROL |  | 6 | 10 | Ω | IOUT = 10 mA, VDD = 18V, TA = +25°C | 3 |
| Rise Time | tR |  |  | 30 | nsec | Figure 3-1, Figure 3-2, TA = +25°C | 3 |
| Fall Time | tF |  |  | 30 | nsec | Figure 3-1, Figure 3-2, TA = +25°C | 3 |
| Delay Time | tD1 |  |  | 50 | nsec | Figure 3-1, Figure 3-2, TA = +25°C | 3 |
| Delay Time | tD2 |  |  | 75 | nsec | Figure 3-1, Figure 3-2, TA = +25°C | 3 |
| Power Supply Current | IS |  |  | 8 | mA | VIN = 3V (Both Inputs), TA = +25°C | 3 |
| Power Supply Current | IS |  |  | 0.4 | mA | VIN = 0V (Both Inputs), TA = +25°C | 3 |
| Logic 1, High Input Voltage | VIH | 2.4 |  |  | V | Over operating temperature range, 4.5V ≤ VDD ≤ 18V | 4 |
| Logic 0, Low Input Voltage | VIL |  |  | 0.8 | V | Over operating temperature range, 4.5V ≤ VDD ≤ 18V | 4 |
| Input Current | IIN | -10 |  | 10 | µA | 0V ≤ VIN ≤ VDD, over operating temperature range | 4 |
| Low Output Voltage | VOL |  |  | 0.025 | V | Over operating temperature range | 4 |
| High Output Resistance | ROH |  | 13 | 20 | Ω | IOUT = 10 mA, VDD = 18V, over operating temperature range | 4 |
| Low Output Resistance | ROL |  | 8 | 15 | Ω | IOUT = 10 mA, VDD = 18V, over operating temperature range | 4 |
| Rise Time | tR |  |  | 60 | nsec | Figure 3-1, Figure 3-2, over operating temperature range | 4 |
| Fall Time | tF |  |  | 60 | nsec | Figure 3-1, Figure 3-2, over operating temperature range | 4 |
| Delay Time | tD1 |  |  | 75 | nsec | Figure 3-1, Figure 3-2, over operating temperature range | 4 |
| Delay Time | tD2 |  |  | 120 | nsec | Figure 3-1, Figure 3-2, over operating temperature range | 4 |
| Power Supply Current | IS |  |  | 12 | mA | VIN = 3V (Both Inputs), over operating temperature range | 4 |
| Power Supply Current | IS |  |  | 0.6 | mA | VIN = 0V (Both Inputs), over operating temperature range | 4 |
| Supply Voltage | VDD |  |  | 20 | V |  | 3 |
| Derating Factor, PDIP |  |  | 8 |  | mW/°C | PDIP | 3 |
| Operating Temperature Range, C Version |  | 0 |  | 70 | °C | C Version | 3 |
| Storage Temperature Range |  | -65 |  | 150 | °C |  | 3 |
| Operating Supply Voltage | VDD | 4.5 |  | 18 | V |  | 1 |
| Peak Output Current | IPK |  | 1.5 |  | A | TA = +25°C | 3 |

## CAD (KiCad official)

- Symbol: `TC426CPA`
- Footprint: `Package_DIP:DIP-8_W7.62mm`
- 3D model: PDIP-8 (KiCad packages3D, STEP)
- 3D model files: `tc426cpa-etched.step` / `tc426cpa-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tc426cpa.step` / `tc426cpa.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/tc426cpa-datasheet.pdf) (18 pp, sha256 `55c8e1e875247e43`, retrieved 2026-10-23, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tc426cpa-datasheet.pdf)