component
TC4081BF
Public Made by Adomby adom
TOSHIBA Logic Gates, SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTC4081BF
TOSHIBA · Logic Gates · SOP-14
TC4081BF from TOSHIBA, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A1 | input | Input A of gate 1; unused inputs must be tied to VDD or VSS. |
| 2 | B1 | input | Input B of gate 1; unused inputs must be tied to VDD or VSS. |
| 3 | X1 | output | Buffered output of gate 1, X = A·B. |
| 4 | X2 | output | Buffered output of gate 2, X = A·B. |
| 5 | B2 | input | Input B of gate 2; unused inputs must be tied to VDD or VSS. |
| 6 | A2 | input | Input A of gate 2; unused inputs must be tied to VDD or VSS. |
| 7 | VSS | power_in | Ground supply pin (VSS = 0 V). |
| 8 | A3 | input | Input A of gate 3; unused inputs must be tied to VDD or VSS. |
| 9 | B3 | input | Input B of gate 3; unused inputs must be tied to VDD or VSS. |
| 10 | X3 | output | Buffered output of gate 3, X = A·B. |
| 11 | X4 | output | Buffered output of gate 4, X = A·B. |
| 12 | B4 | input | Input B of gate 4; unused inputs must be tied to VDD or VSS. |
| 13 | A4 | input | Input A of gate 4; unused inputs must be tied to VDD or VSS. |
| 14 | VDD | power_in | Positive supply pin, operating range 3 to 18 V (absolute maximum VSS + 20 V). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | TOSHIBA |
| Package | SOP-14 |
| Category | Logic |
| Pins | 14 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| DC supply voltage | VDD | -0.5 | 20 | V | Referenced to VSS (VSS − 0.5 to VSS + 20 V) | 2 | |
| Input voltage | VIN | -0.5 | V | VSS − 0.5 to VDD + 0.5 V; upper limit set by VDD | 2 | ||
| Output voltage | VOUT | -0.5 | V | VSS − 0.5 to VDD + 0.5 V; upper limit set by VDD | 2 | ||
| DC input current | IIN | -10 | 10 | mA | 2 | ||
| Power dissipation | PD | 180 | mW | SOIC package (300 mW for DIP) | 2 | ||
| Operating temperature range | Tope | -40 | 85 | °C | 2 | ||
| Storage temperature range | Tstg | -65 | 150 | °C | 2 | ||
| DC supply voltage (operating range) | VDD | 3 | 18 | V | VSS = 0 V | 2 | |
| Input voltage (operating range) | VIN | 0 | V | VSS = 0 V; upper limit VDD | 2 | ||
| High-level output voltage | VOH | 4.95 | 5 | V | /IOUT/ < 1 μA, VIN = VSS, VDD = 5 V (typ at 25°C) | 3 | |
| High-level output voltage | VOH | 9.95 | 10 | V | /IOUT/ < 1 μA, VIN = VSS, VDD = 10 V (typ at 25°C) | 3 | |
| High-level output voltage | VOH | 14.95 | 15 | V | /IOUT/ < 1 μA, VIN = VSS, VDD = 15 V (typ at 25°C) | 3 | |
| Low-level output voltage | VOL | 0 | 0.05 | V | /IOUT/ < 1 μA, VIN = VSS, VDD = 5 V (typ at 25°C) | 3 | |
| Output high current | IOH | -0.51 | -1 | mA | VIN = VDD; VOH = 4.6 V; VDD = 5 V; 25°C | 3 | |
| Output high current | IOH | -0.42 | mA | VIN = VDD; VOH = 4.6 V; VDD = 5 V; 85°C | 3 | ||
| Output high current | IOH | -2.1 | -4 | mA | VIN = VDD; VOH = 2.5 V; VDD = 5 V; 25°C | 3 | |
| Output high current | IOH | -1.7 | mA | VIN = VDD; VOH = 2.5 V; VDD = 5 V; 85°C | 3 | ||
| Output high current | IOH | -1.3 | -2.2 | mA | VIN = VDD; VOH = 9.5 V; VDD = 10 V; 25°C | 3 | |
| Output high current | IOH | -1.1 | mA | VIN = VDD; VOH = 9.5 V; VDD = 10 V; 85°C | 3 | ||
| Output high current | IOH | -3.4 | -9 | mA | VIN = VDD; VOH = 13.5 V; VDD = 15 V; 25°C | 3 | |
| Output high current | IOH | -2.8 | mA | VIN = VDD; VOH = 13.5 V; VDD = 15 V; 85°C | 3 | ||
| Output low current | IOL | 3.5 | mA | VIN = VSS, VDD; VOUT = 0.5 V, 4.5 V; VDD = 5 V; −40°C | 3 | ||
| Output low current | IOL | 7 | mA | VIN = VSS, VDD; VOUT = 1.0 V, 9.0 V; VDD = 10 V; −40°C | 3 | ||
| Output low current | IOL | 11 | mA | VIN = VSS, VDD; VOUT = 1.5 V, 13.5 V; VDD = 15 V; −40°C | 3 | ||
| “H” level input current | IIH | 0.1 | μA | VIH = 18 V; VDD = 18 V; −40°C | 3 | ||
| “H” level input current | IIH | 1 | μA | VIH = 18 V; VDD = 18 V; 85°C | 3 | ||
| “L” level input current | IIL | -0.1 | μA | VIL = 0 V; VDD = 18 V; −40°C | 3 | ||
| “L” level input current | IIL | -1 | μA | VIL = 0 V; VDD = 18 V; 85°C | 3 | ||
| Quiescent supply current | IDD | 0.25 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 5 V; −40°C | 3 | ||
| Quiescent supply current | IDD | 0.001 | 0.25 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 5 V; 25°C | 3 | |
| Quiescent supply current | IDD | 7.5 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 5 V; 85°C | 3 | ||
| Quiescent supply current | IDD | 0.5 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 10 V; −40°C | 3 | ||
| Quiescent supply current | IDD | 0.001 | 0.5 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 10 V; 25°C | 3 | |
| Quiescent supply current | IDD | 15 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 10 V; 85°C | 3 | ||
| Quiescent supply current | IDD | 1 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 15 V; −40°C | 3 | ||
| Quiescent supply current | IDD | 0.002 | 1 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 15 V; 25°C | 3 | |
| Quiescent supply current | IDD | 30 | μA | VIN = VSS, VDD (all valid input combinations); VDD = 15 V; 85°C | 3 | ||
| Output transition time (low to high) | tTLH | 70 | 200 | ns | VDD = 5 V; CL = 50 pF; Ta = 25°C | 4 | |
| Output transition time (low to high) | tTLH | 35 | 100 | ns | VDD = 10 V; CL = 50 pF; Ta = 25°C | 4 | |
| Output transition time (low to high) | tTLH | 30 | 80 | ns | VDD = 15 V; CL = 50 pF; Ta = 25°C | 4 | |
| Output transition time (high to low) | tTHL | 70 | 200 | ns | VDD = 5 V; CL = 50 pF; Ta = 25°C | 4 | |
| Output transition time (high to low) | tTHL | 35 | 100 | ns | VDD = 10 V; CL = 50 pF; Ta = 25°C | 4 | |
| Output transition time (high to low) | tTHL | 30 | 80 | ns | VDD = 15 V; CL = 50 pF; Ta = 25°C | 4 | |
| Propagation delay time (low to high) | tpLH | 65 | 200 | ns | VDD = 5 V; CL = 50 pF; Ta = 25°C | 4 | |
| Propagation delay time (low to high) | tpLH | 30 | 100 | ns | VDD = 10 V; CL = 50 pF; Ta = 25°C | 4 | |
| Propagation delay time (low to high) | tpLH | 25 | 80 | ns | VDD = 15 V; CL = 50 pF; Ta = 25°C | 4 | |
| Propagation delay time (high to low) | tpHL | 65 | 200 | ns | VDD = 5 V; CL = 50 pF; Ta = 25°C | 4 | |
| Propagation delay time (high to low) | tpHL | 30 | 100 | ns | VDD = 10 V; CL = 50 pF; Ta = 25°C | 4 | |
| Propagation delay time (high to low) | tpHL | 25 | 80 | ns | VDD = 15 V; CL = 50 pF; Ta = 25°C | 4 | |
| Input capacitance | CIN | 5 | 7.5 | pF | 4 |
CAD (KiCad official)
- Symbol:
TC4081BF - Footprint:
Package_SO:SOIC-14_3.9x8.7mm_P1.27mm - 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files:
tc4081bf-etched.step/tc4081bf-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc4081bf.step/tc4081bf.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: TOSHIBA datasheet (7 pp, sha256
353ccdb861a57b2b, retrieved 2026-10-19, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).