component
TC1411NEOA
Public Made by Adomby adom
Microchip Tech Gate Drivers, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownTC1411NEOA
Microchip Tech · Gate Drivers · SOIC-8
TC1411NEOA from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Bias supply for the MOSFET driver, rated 4.5V to 16V with respect to the ground pin; bypass to ground with a local ceramic capacitor (1.0 µF suggested). |
| 2 | IN | input | High-impedance, TTL/CMOS-compatible control input with 300 mV of hysteresis between the high and low thresholds. |
| 3 | NC | unconnected | No internal connection. |
| 4 | GND | power_in | Ground return path for the bias current and high-peak discharge currents; tie to a ground plane or use very short traces to the bias supply return. |
| 5 | GND | power_in | Ground return path for the bias current and high-peak discharge currents; tie to a ground plane or use very short traces to the bias supply return, and connect together with pin 4. |
| 6 | OUT | output | CMOS push-pull output, common to pin 7, capable of driving a capacitive load with 1A peak current; duplicate pins must be connected together. |
| 7 | OUT | output | CMOS push-pull output, common to pin 6, capable of driving a capacitive load with 1A peak current; duplicate pins must be connected together. |
| 8 | VDD | power_in | Bias supply for the MOSFET driver, rated 4.5V to 16V with respect to the ground pin; connect together with pin 1. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Logic '1', High Input Voltage | VIH | 2 | V | 3 | |||
| Logic '0', Low Input Voltage | VIL | 0.8 | V | 3 | |||
| Input Current | IIN | -1 | 1 | µA | 0V ≤ VIN ≤ VDD, TA = +25°C | 3 | |
| Input Current | IIN | -10 | 10 | µA | -40°C ≤ TA ≤ +85°C | 3 | |
| Low Output Voltage | VOL | 0.025 | V | DC Test | 3 | ||
| Output Resistance (E grade) | RO | 10 | 14 | Ω | -40°C ≤ TA ≤ +85°C | 3 | |
| Rise Time | tR | 29 | 40 | ns | -40°C ≤ TA ≤ +85°C, Figure 4-1 | 3 | |
| Fall Time | tF | 29 | 40 | ns | -40°C ≤ TA ≤ +85°C, Figure 4-1 | 3 | |
| Delay Time | tD1 | 35 | 45 | ns | -40°C ≤ TA ≤ +85°C, Figure 4-1 | 3 | |
| Power Supply Current | IS | 0.5 | 1 | mA | VIN = 3V, VDD = 16V | 4 | |
| Power Supply Current | IS | 0.1 | 0.15 | mA | VIN = 0V | 4 | |
| Supply Voltage | VDD | 4.5 | 16 | V | 3 | ||
| Specified Temperature Range (E) | TA | -40 | 85 | ºC | 4 | ||
| Maximum Junction Temperature | TJ | 150 | ºC | 4 | |||
| Storage Temperature Range | TA | -65 | 150 | ºC | 4 | ||
| Supply Voltage | 20 | V | 3 | ||||
| Thermal Resistance, 8L-SOIC | JA | 149.5 | ºC/W | 4 |
CAD (KiCad official)
- Symbol:
TC1411NEOA - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
tc1411neoa-etched.step/tc1411neoa-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);tc1411neoa.step/tc1411neoa.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Microchip Tech datasheet (22 pp, sha256
747e813695925807, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).