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tc1410eoa713

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Microchip Isolators - Gate Drivers, SOIC-8. Datasheet-verified pinout, KiCad symbol/footprint/3D.

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README

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TC1410EOA713

Microchip · Isolators - Gate Drivers · SOIC-8

TC1410EOA713 from Microchip, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Bias supply input, 4.5V to 16V. Common to pin 8 - both VDD pins must be tied together. Bypass to GND with a local ceramic capacitor (~1.0 µF recommended, sized to the load being driven).
2 IN input High-impedance TTL/CMOS-compatible control input. VIH ≥ 2.0V, VIL ≤ 0.8V, with ~300 mV of hysteresis to prevent output glitching on slow input edges. Withstands negative inputs to −5V.
3 NC unconnected No internal connection. Leave floating or tie to ground for noise reduction.
4 GND power_in Ground return for bias current and for the high peak currents that discharge the load capacitor. Common to pin 5 - both GND pins must be tied together to a low-impedance ground plane.
5 GND power_in Ground return, common to pin 4. Both GND pins must be tied together. Tolerates up to ±5V of ground noise spiking without damage.
6 OUT output CMOS push-pull driver output, 0.5A peak. RO ≈ 16 Ω typical at VDD = 16V. Inverted with respect to IN (TC1410 is the inverting variant). Common to pin 7 - both OUT pins must be tied together to share the output current. Withstands up to 500 mA of reverse current forced back into the output.
7 OUT output CMOS push-pull driver output, common to pin 6. Both OUT pins must be tied together for proper operation and full 0.5A peak drive.
8 VDD power_in Bias supply input, 4.5V to 16V, common to pin 1. Both VDD pins must be tied together. Absolute maximum supply voltage is +20V.

Key specifications

Parameter Value
Manufacturer Microchip
Package SOIC-8
Category PMIC
Pins 8

Ordering variants

  • TC1410EOA713
  • TC1410EOA713UA
  • TC1410EOA713UA713
  • TC1410EOA713PA

CAD (KiCad official)

  • Symbol: TC1410EOA713
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: tc1410eoa713-etched.step / tc1410eoa713-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); tc1410eoa713.step / tc1410eoa713.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Microchip datasheet (None pp, sha256 fb8f5c2b81de935c, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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