# TC1321EOA

**Microchip Tech** · Digital To Analog Converters (DACs) · SOIC-8

TC1321EOA from Microchip Tech, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VREF | power_in | Voltage reference input pin, buffered high-impedance input accepting 0V to 1.2V below VDD (VDD - 1.2V) with less than 1 µA leakage. |
| 2 | SDA | bidirectional | Bi-directional SMBus/I2C serial data input/output pin; must be connected to VDD or VSS when the serial port is inactive. |
| 3 | SCL | input | SMBus/I2C serial clock input that clocks data into and out of the TC1321; must be connected to VDD or VSS when the serial port is inactive. |
| 4 | VSS | power_in | Supply power ground reference pin. |
| 5 | VOUT | output | Buffered DAC analog voltage output, a function of VREF and the DATA register contents, with 2 mA typical source/sink output current. |
| 6 | NC | unconnected | No connection; there is no internal connection at this pin. |
| 7 | DAC-OUT | output | Unbuffered DAC analog voltage output that must be connected only to a high-impedance node. |
| 8 | VDD | power_in | Positive power supply input pin, operating range 2.7V to 5.5V (absolute maximum +6V). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Microchip Tech |
| Package | SOIC-8 |
| Category | ADC/DAC/Data Conversion |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply Voltage | VDD | 2.7 |  | 5.5 | V |  | 3 |
| Operating Current | IDD |  | 350 | 500 | µA | VDD = 5.5V, VREF = 1.2V, Serial Port Inactive (Note 1) | 3 |
| Standby Supply Current | IDD-STANDBY |  | 0.1 | 1 | µA | VDD = 3.3V, Serial Port Inactive (Note 1) | 3 |
| Integral Non-Linearity at FS | INL | -4 |  | 4 | LSB | TA = +25°C (Note 2) | 3 |
| Full Scale Error | FSE | -3 |  | 3 | %FS |  | 3 |
| Differential Non-Linearity | DNL | -1 |  | 2 | LSB | TA = +25°C, All Codes (Note 2) | 3 |
| Offset Error at VOUT | VOS | -8 | 0.3 | 8 | mV | (Note 2) | 3 |
| Voltage Reference Range | VREF | 0 |  | 3 | V | 0 to VDD, 1.2 | 3 |
| Reference Input Leakage Current | IREF | -1 |  | 1 | µA |  | 3 |
| Output Short-Circuit Current (Source) | ISC |  | 30 | 50 | mA | VDD = 5.5V, Source | 3 |
| Output Short-Circuit Current (Sink) | ISC |  | 20 | 50 | mA | VDD = 5.5V, Sink | 3 |
| Logic Input High | VIH | 2.4 |  |  | V |  | 3 |
| Logic Input Low | VIL |  |  | 0.6 | V |  | 3 |
| SDA Output Low | VOL |  |  | 0.4 | V | IOL = 3 mA (Sinking Current) | 3 |
| SDA Output Low | VOL |  |  | 0.6 | V | IOL = 6 mA | 3 |
| I/O Leakage | ILEAK | -1 |  | 1 | µA |  | 4 |
| SMBus Clock Frequency | fSMB | 10 |  | 100 | kHz |  | 4 |
| Bus Free Time Prior to New Transition | tIDLE | 4.7 |  |  | µs |  | 4 |
| START Condition Hold Time | tH(START) | 4 |  |  | µs |  | 4 |
| START Condition Setup Time | tSU(START) | 4.7 |  |  | µs | 90% SCL to 10% SDA (for Repeated START Condition) | 4 |
| STOP Condition Setup Time | tSU(STOP) | 4 |  |  | µs |  | 4 |
| Data In Hold Time | tH-DATA | 100 |  |  | ns |  | 4 |
| Data In Setup Time | tSU-DATA | 100 |  |  | ns |  | 4 |
| Low Clock Period | tLOW | 4.7 |  |  | µs | 10% to 10% | 4 |
| High Clock Period | tHIGH | 4 |  |  | µs | 90% to 90% | 4 |
| SMBus Fall Time | tF |  |  | 300 | ns | 90% to 10% | 4 |
| SMBus Rise Time | tR |  |  | 1000 | ns | 10% to 90% | 4 |
| Operating Temperature Range | TA | -40 |  | 85 | °C |  | 4 |
| Storage Temperature Range | TA | -65 |  | 150 | °C |  | 4 |
| Supply Voltage (Absolute Maximum) | VDD |  |  | 6 | V |  | 3 |
| Current on any Pin |  | -50 |  | 50 | mA |  | 3 |
| Thermal Resistance, 8L SOIC | θJA |  | 149.5 |  | °C/W |  | 4 |
| Package Thermal Resistance (Absolute Maximum section) | θJA |  | 330 |  | °C/W |  | 3 |
| Offset Error Tempco at VOUT | TCVOS |  | 10 |  | µv/°C |  | 3 |
| Power Supply Rejection Ratio | PSRR |  | 80 |  | dB | VDD at DC | 3 |
| Output Resistance @ VOUT | ROUT |  | 5 |  | Ω |  | 3 |
| Output Current (Source or Sink) | IOUT |  | 2 |  | mA |  | 3 |
| Voltage Output Slew Rate | SR |  | 0.8 |  | V/µs |  | 3 |
| Output Voltage Full Scale Settling Time | tSETTLE |  | 10 |  | µs |  | 3 |
| Wake-up Time | tWU |  | 20 |  | µs |  | 3 |
| Power-on Reset Delay | tPOR |  | 500 |  | µs | VDD ≥ VPOR (Rising Edge) | 4 |
| Resolution |  |  | 10 |  | Bits |  | 3 |

## CAD (KiCad official)

- Symbol: `TC1321EOA`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `tc1321eoa-etched.step` / `tc1321eoa-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `tc1321eoa.step` / `tc1321eoa.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Microchip Tech datasheet](docs/tc1321eoa-datasheet.pdf) (24 pp, sha256 `3b606b8976e55c8b`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/tc1321eoa-datasheet.pdf)